Patent US2960845A successfully refreshed from Google Patents.
Patent US5163049A successfully refreshed from Google Patents.
US5163049A
Expired / Lapsed
US
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Method for assuring data-string-consistency independent of software
Assignee: Honeywell Inc
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Filing: 1990-08-10
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Granted: 1992-11-10
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Expires: 2010-08-10
Abstract
Abstract An improved distributed processing system for controlling the transfer of data between a terminal controller and a subsystem is described where the improvement insures wordstring consistency in a manner which is completely transparent to the subscriber subsystem. In particular, data is transferred, via a dual-bank, dual-port terminal memory where the bank selection is controlled such that any wordstring transfers between the terminal memory and the terminal controller are constrained to involve a different bank than transfers between the terminal memory and its associated subscriber subsystem. A wordstring log associated with control arbitration logic contains the dynamic state of the bank assignments for each wordstring. Two flag bits in the wordstring log provide information to the control/arbitration logic, allowing it to manage the bank selection of the terminal memory.
Inventors
- 👤 Clarence S. Smith
- 👤 Larry J. Yount
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:38
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/40
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
194 words
In a distributed data processing system of the type including a plurality of subscribers, each subscriber operatively coupled to an autonomous terminal controller (ATC), each of said ATCs including a terminal memory partitioned into a first and second bank, each of said ATCs communicating over a serial data bus using a packet protocol, a method for assuring data integrity at the interface between any one of said subscribers and its associated ATC comprising the steps of: (a) transferring a first packet from a first of said plurality of subscribers to a first terminal memory; (b) decoding a portion of said first packet using a decoding means for generating an output corresponding to said portion, said decoding means selecting one of said first or second banks of said first terminal memory as a function of said output; (c) writing said first packet into said selected bank of said first terminal memory; and (d) transferring said first packet from said selected bank of said first terminal memory to said serial data bus while concurrently transferring a second packet from said first of said plurality of subscribers to said other unselected bank of said first terminal memory.
Claim 2
Dependent Claim
194 words
In a distributed data processing system of the type including a plurality of subscribers, each subscriber operatively coupled to an autonomous terminal controller (ATC), each of said ATCs including a terminal memory partitioned into a first and second bank, each of said ATCs communicating over a serial data bus using a packet protocol, a method for assuring data integrity at the interface between any one of said subscribers and its associated ATC comprising the steps of: (a) transferring a first packet from a first of said plurality of subscribers to a first terminal memory; (b) decoding a portion of said first packet using a decoding means for generating an output corresponding to said portion, said decoding means selecting one of said first or second banks of said first terminal memory as a function of said output; (c) writing said first packet into said selected bank of said first terminal memory; and (d) transferring said first packet from said selected bank of said first terminal memory to said serial data bus while concurrently transferring a second packet from said first of said plurality of subscribers to said other unselected bank of said first terminal memory.
Claim 3
Dependent Claim
53 words
The method as in claim 1 and further including the steps of: (e) transferring said first packet from said serial data bus to a first bank of a second terminal memory while transferring a third packet in a second bank of said second terminal memory to a second of said plurality of subscribers.
Claim 4
Dependent Claim
208 words
In a distributed data processing system of the type including a bi-directional digital data bus; a plurality of subscriber subsystems; a plurality of autonomous terminal controllers independently coupling said plurality of subscriber systems to said bi-directional digital data bus whereby digital data in a packet protocol may be transmitted from one subscriber system to another; each of said autonomous terminal controllers including a terminal memory partitioned into first and second banks for storing digital data at addressable locations therein; the improvement comprising: (a) means for transferring a first packet from a first of said plurality of subscriber subsystems to one of said banks of a first terminal memory; (b) means for decoding a portion of said first packet and generating an output corresponding to said portion, said means for decoding selecting one of said banks of said first terminal memory as a function of said output; (c) means for writing said first packet into said selected bank of said first terminal memory; and (d) means for transferring said first packet from said selected bank of said first terminal memory to said bi-directional data bus while concurrently transferring a second packet from said first of said plurality of subscriber subsystems to said unselected bank of said first terminal memory.
Claim 5
Dependent Claim
208 words
In a distributed data processing system of the type including a bi-directional digital data bus; a plurality of subscriber subsystems; a plurality of autonomous terminal controllers independently coupling said plurality of subscriber systems to said bi-directional digital data bus whereby digital data in a packet protocol may be transmitted from one subscriber system to another; each of said autonomous terminal controllers including a terminal memory partitioned into first and second banks for storing digital data at addressable locations therein; the improvement comprising: (a) means for transferring a first packet from a first of said plurality of subscriber subsystems to one of said banks of a first terminal memory; (b) means for decoding a portion of said first packet and generating an output corresponding to said portion, said means for decoding selecting one of said banks of said first terminal memory as a function of said output; (c) means for writing said first packet into said selected bank of said first terminal memory; and (d) means for transferring said first packet from said selected bank of said first terminal memory to said bi-directional data bus while concurrently transferring a second packet from said first of said plurality of subscriber subsystems to said unselected bank of said first terminal memory.
Claim 6
Dependent Claim
56 words
The distributed data processing system as in claim 3 and further including: (e) means for transferring said first packet from said bi-directional data bus to a first bank of a second terminal memory while transferring a third packet in a second bank of said second terminal memory to a second of said plurality of subscriber subsystems.
Claim 7
Dependent Claim
23 words
The distributed data processing system as in claim 3 wherein said means for decoding comprises discrete components to form an arbitration logic circuit.
Claim 8
Dependent Claim
57 words
The distributed data processing system as in claim 5 wherein said arbitration logic circuit comprises a decoder which decodes an address portion of said digital data, and further comprises a selector responsive to said decoder for enabling said first and second banks of said first terminal memory depending on the decoded address portion of said digital data.
Claim 9
Dependent Claim
20 words
The distributed data processing system of claim 6 wherein said decoder comprises a wordstring log including a memory integrated circuit.
Claim 10
Dependent Claim
18 words
The distributed data processing system of claim 7 wherein said memory integrated circuit is a dual-port static RAM.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |