US5162890A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked capacitor with sidewall insulation
Assignee: UMC Japan Co Ltd
•
Filing: 1991-04-05
•
Granted: 1992-11-10
•
Expires: 2011-04-05
Abstract
Abstract In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.
Inventors
- 👤 Douglas B. Butler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D1/00; H10D1/60; H10D1/68; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
213 words
A stacked capacitor arrangement for an integrated circuit of the type having a substrate, a first capacitor and a second capacitor formed on top of said first capacitor, said first and second capacitors being coupled together, wherein the improvement comprises: a common plate shared by said first and second capacitors; a lower plate which comprises a conductive region in the substrate; an upper plate above the common plate, the common plate and upper plate being located above the lower plate; a first dielectric layer located between the lower plate and the common plate, and a second dielectric layer located between the common plate and the upper plate; a step having a substantially continuous and substantially vertical sidewall formed by sidewalls of the common plate, the upper plate, and the dielectric therebetween, a lateral portion of the upper plate being at the top of the step; a stick of insulation located along the sidewall of said step, said insulation stick extending continuously up said sidewall thereby to insulate said common plate at the sidewall formed therein; and a conductive layer electrically coupled to and extending from the lateral portion of the upper plate, over the stick of insulation, to the bottom of the step for electrically coupling the upper plate to the lower plate.
Claim 2
Dependent Claim
213 words
A stacked capacitor arrangement for an integrated circuit of the type having a substrate, a first capacitor and a second capacitor formed on top of said first capacitor, said first and second capacitors being coupled together, wherein the improvement comprises: a common plate shared by said first and second capacitors; a lower plate which comprises a conductive region in the substrate; an upper plate above the common plate, the common plate and upper plate being located above the lower plate; a first dielectric layer located between the lower plate and the common plate, and a second dielectric layer located between the common plate and the upper plate; a step having a substantially continuous and substantially vertical sidewall formed by sidewalls of the common plate, the upper plate, and the dielectric therebetween, a lateral portion of the upper plate being at the top of the step; a stick of insulation located along the sidewall of said step, said insulation stick extending continuously up said sidewall thereby to insulate said common plate at the sidewall formed therein; and a conductive layer electrically coupled to and extending from the lateral portion of the upper plate, over the stick of insulation, to the bottom of the step for electrically coupling the upper plate to the lower plate.
Claim 3
Dependent Claim
22 words
The stacked capacitor arrangement as described in claim 1 wherein said common plate is a field shield layer extending beyond said arrangement.
Claim 4
Dependent Claim
35 words
The stacked capacitor arrangement as described in claim 1 further comprising a pass transistor coupled to the stacked first and second capacitors, whereby a memory cell is formed of the capacitor arrangement and pass transistor.
Claim 5
Dependent Claim
29 words
The stacked capacitor arrangement as described in claim 3 wherein said common plate is a field shield layer extending beyond said memory cell and connected to a reference potential.
Claim 6
Dependent Claim
71 words
The stacked capacitor arrangement as described in claim 1 further comprising: a planar layer of an insulating material located upon an upper surface of only a portion of the upper plate; a planar polysilicon layer located on top of said layer of insulating material; and a further layer of an insulating layer located on top of said polysilicon layer, said layers over the upper plate forming a second substantially vertical sidewall.
Claim 7
Dependent Claim
16 words
The stacked capacitor arrangement as described in claim 5 wherein said planar polysilicon layer is undoped.
Claim 8
Dependent Claim
20 words
The capacitor arrangement of claim 1 wherein said conductive layer contacts only a portion of said upper plate upper surface.
Claim 9
Dependent Claim
27 words
The capacitor arrangement of claim 7 wherein said upper surface of said upper plate is in contact with a further layer of insulation and said conductive layer.
Claim 10
Dependent Claim
27 words
The stacked capacitor arrangement of claim 1 wherein said upper plate is planar and said common plate is planar in the vicinity of said stacked capacitor arrangement.
Claim 11
Dependent Claim
14 words
The stacked capacitor arrangement of claim 9 wherein said common plate comprises doped polysilicon.
Claim 12
Dependent Claim
51 words
The stacked capacitor arrangement of claim 9 wherein said step comprises an upper planar portion, a lower planar portion, and said sidewall, said lower planar portion being proximate to an upper surface of said substrate, said upper planar step portion comprising only parts of an upper surface of said upper plate.
Claim 13
Dependent Claim
139 words
A capacitor arrangement for an integrated circuit comprising: a central capacitor plate, an upper capacitor plate and a dielectric therebetween, whereby a capacitor is formed; a step having a substantially continuous, substantially vertical sidewall formed by sidewalls of the central capacitor plate, the upper plate, and the dielectric therebetween, a lateral portion of the upper plate being at the top of the step; a stick of insulation located along the sidewall of said step, said insulation stick extending continuously up said sidewall thereby to insulate said central plate at the sidewall formed therein; and a conductive layer extending from the lateral portion of the upper plate, over the stick of insulation, to the bottom of the step for electrically coupling the upper plate to a member at the bottom of the step without coupling it to the central plate.
Claim 14
Dependent Claim
139 words
A capacitor arrangement for an integrated circuit comprising: a central capacitor plate, an upper capacitor plate and a dielectric therebetween, whereby a capacitor is formed; a step having a substantially continuous, substantially vertical sidewall formed by sidewalls of the central capacitor plate, the upper plate, and the dielectric therebetween, a lateral portion of the upper plate being at the top of the step; a stick of insulation located along the sidewall of said step, said insulation stick extending continuously up said sidewall thereby to insulate said central plate at the sidewall formed therein; and a conductive layer extending from the lateral portion of the upper plate, over the stick of insulation, to the bottom of the step for electrically coupling the upper plate to a member at the bottom of the step without coupling it to the central plate.
Claim 15
Dependent Claim
17 words
The capacitor arrangement as described in claim 12 further comprising a pass transistor coupled to the capacitor.
Claim 16
Dependent Claim
34 words
The capacitor arrangement as described in claim 13 and further comprising a lower capacitor plate located below the central plate, wherein said upper and lower plates are connected in series to said pass transistor.
Claim 17
Dependent Claim
39 words
The capacitor arrangement as described in claim 13 wherein said arrangement and pass transistor form a memory cell, and wherein said central plate is a field shield layer extending beyond the memory cell and coupled to a fixed potential.
Claim 18
Dependent Claim
49 words
The capacitor arrangement for an integrated circuit as described in claim 12 further comprising a lower plate which comprises a conductive region in the substrate, said lower plate being located below said central plate and separated therefrom by a lower dielectric layer, whereby a stacked capacitor arrangement is formed.
Claim 19
Dependent Claim
32 words
The capacitor arrangement as described in claim 16 further comprising an insulating material over the upper plate; a polysilicon layer over said insulating material; and another insulating layer over said polysilicon layer.
Claim 20
Dependent Claim
21 words
The capacitor arrangement as described in claim 17 wherein said layers over the upper plate form a second substantially vertical sidewall.
Claim 21
Dependent Claim
14 words
The capacitor arrangement as described in claim 17 wherein said polysilicon layer is undoped.
References Cited (Backward Citations)
US4570331A
Cited
US4721987A
Cited
US4700457A
Cited
US4686000A
Cited
US4685197A
Cited
US4899203A
Cited
US4864464A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |