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US5162880A
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Nonvolatile memory cell having gate insulation film with carrier traps therein
Assignee: Toshiba Corp
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Filing: 1990-09-27
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Granted: 1992-11-10
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Expires: 2010-09-27
Abstract
Abstract A nonvolatile memory cell comprises a semiconductor substrate of first conduction type, a high-concentration impurity region of second conduction type formed on the semiconductor substrate and connected to a bit line, an insulation film in which carrier traps are formed, and a gate electrode that is opposite the high-concentration impurity region across the insulation film and connected to a word line. Carriers are captured by, and released from, the carrier traps formed in the insulation film, in response to bias voltages applied to the word and bit lines. Information stored in the memory cell depends on whether or not the carrier traps are holding carriers. The information is read out of the memory cell as the difference of a tunneling current flowing between the semiconductor substrate and the high-concentration impurity region.
Inventors
- 👤 Hiroaki Hazama
- 👤 Kazumi Nishinohara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:55
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/812; H10B; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
186 words
A nonvolatile memory cell comprising: (a) a semiconductor substrate of a first conduction type; (b) a high-concentration impurity region of a second conduction type formed on said semiconductor substrate of first conduction type and connected to a bit line; (c) a gate insulation film formed on said semiconductor substrate; (d) carrier traps formed in said gate insulation film; (e) a gate electrode formed on said gate insulation film and connected to a word line, at least a part of said gate electrode being opposite said high-concentration impurity region across said gate insulation film and (f) means for applying bias voltages to the word and bit lines to control carriers that are captured by and released from said carrier traps formed in said gate insulation film between said high-concentration impurity region and said gate electrode, the nonvolatile memory cell storing information therein, depending on the capture or release of carriers, the information stored in the nonvolatile memory cell being read according to the degree of difference of a tunneling current flowing between said semiconductor substrate and said high-concentration impurity region with and without the capture of carriers.
Claim 2
Dependent Claim
186 words
A nonvolatile memory cell comprising: (a) a semiconductor substrate of a first conduction type; (b) a high-concentration impurity region of a second conduction type formed on said semiconductor substrate of first conduction type and connected to a bit line; (c) a gate insulation film formed on said semiconductor substrate; (d) carrier traps formed in said gate insulation film; (e) a gate electrode formed on said gate insulation film and connected to a word line, at least a part of said gate electrode being opposite said high-concentration impurity region across said gate insulation film and (f) means for applying bias voltages to the word and bit lines to control carriers that are captured by and released from said carrier traps formed in said gate insulation film between said high-concentration impurity region and said gate electrode, the nonvolatile memory cell storing information therein, depending on the capture or release of carriers, the information stored in the nonvolatile memory cell being read according to the degree of difference of a tunneling current flowing between said semiconductor substrate and said high-concentration impurity region with and without the capture of carriers.
Claim 3
Dependent Claim
61 words
The nonvolatile memory cell as claimed in claim 1, wherein an amount of the tunneling current flowing between said semiconductor substrate and said high-concentration impurity region in an area where said gate electrode faces said high-concentration impurity region across said gate insulation film drastically changes depending on whether or not said carrier traps in said gate insulation film are holding carriers.
Claim 4
Dependent Claim
23 words
The nonvolatile memory cell as claimed in claim 2, wherein the first conduction type is P, and the second conduction type is N.
Claim 5
Dependent Claim
29 words
The nonvolatile memory cell as claimed in claim 3, wherein said gate insulation film is a silicon oxide film involving carrier traps of about 5×10 12 cm -2 .
Claim 6
Dependent Claim
59 words
The nonvolatile memory cell as claimed in claim 1, wherein a material is deposited in a part of said high-concentration impurity region so that said part may have a different band gap, said part being located in the area where said gate electrode faces said high-concentration impurity region across said gate insulation film and where a tunneling current occurs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |