Field-effect compound semiconductive transistor with GaAs gate to increase barrier height and reduce turn-on threshold

Claim 2

A field-effect transistor comprising: a substrate of a semi-insulating material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a barrier layer of a wide bandgap semiconductive material disposed on said channel region; a gate layer of a semiconductor material of a first conductivity type disposed on said barrier layer; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped semiconductive material of said first conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of doped semiconductor material of said first conductivity type disposed on said second layer, said third layer contacting said channel region, said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.

Claim 3

The field-effect transistor of claim 1 wherein said first conductivity type is p-type.

Claim 4

A field-effect transistor, comprising: a semi-insulating substrate of a compound semiconductive material of a III-V type; a buffer layer disposed on said substrate and comprising a compound semiconductive material of III-V type; a channel region disposed on said buffer layer and comprising a narrow band gap semiconductive material; a barrier layer disposed on said channel region and comprising a compound semiconductive material of III-V type; a gate layer disposed on said barrier layer and comprising a semiconductive material of a first conductive type; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped compound semiconductive material of III-V type of said conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of compound semiconductive material of III-V type of said first conductivity type disposed on said second layer, said third layer contacting said channel region and said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.

Claim 5

A field-effect transistor, comprising: a semi-insulating substrate of a compound semiconductive material of a III-V type; a buffer layer disposed on said substrate and comprising a compound semiconductive material of III-V type; a channel region disposed on said buffer layer and comprising a narrow band gap semiconductive material; a barrier layer disposed on said channel region and comprising a compound semiconductive material of III-V type; a gate layer disposed on said barrier layer and comprising a semiconductive material of a first conductive type; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped compound semiconductive material of III-V type of said conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of compound semiconductive material of III-V type of said first conductivity type disposed on said second layer, said third layer contacting said channel region and said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.

Claim 6

The field-effect transistor of claim 3 wherein said first conductivity type is p-type.

Claim 7

The field-effect transistor of claim 3 further including means, coupled to said first layer, for adjusting a threshold voltage of said field-effect transistor.

Claim 8

A field-effect transistor of a first conductivity type, comprising: a substrate of a semi-insulating material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a source region of said first conductivity type in contact with a first end of said channel region; a drain region of said first conductivity type in contact with a second end of said channel region; a gate region disposed above said channel; a gate metal contact disposed on said gate region to form an ohmic contact therewith, said buffer layer including a first layer of doped semiconductor material of a second conductivity type opposite said first conductivity type and disposed on said substrate, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of semiconductive material of predominantly said second conductivity type in contact with said channel region.

Claim 9

A field-effect transistor of a first conductivity type, comprising: a substrate of a semi-insulating material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a source region of said first conductivity type in contact with a first end of said channel region; a drain region of said first conductivity type in contact with a second end of said channel region; a gate region disposed above said channel; a gate metal contact disposed on said gate region to form an ohmic contact therewith, said buffer layer including a first layer of doped semiconductor material of a second conductivity type opposite said first conductivity type and disposed on said substrate, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of semiconductive material of predominantly said second conductivity type in contact with said channel region.

Claim 10

The field-effect transistor of claim 6 in which the channel region includes a fourth layer adjacent the third layer, one of said third and fourth layers including doping to provide carriers of the first conductivity type for the channel region.

Claim 11

The field-effect transistor of claim 6, in which: the substrate includes predominantly a first group III-V compound semiconductor; the channel region includes on the third layer a fourth layer of a second group III-V compound semiconductor of the first conductivity type, said third and fourth layers forming a heterojunction; and the gate region comprising at least one layer of a group III-V compound semiconductor of the second conductivity type.

Claim 12

A field-effect transistor comprising: a substrate of a compound semiconductive material of a III-V type having a first bandgap; a source region of a second conductivity type opposite a first conductivity type disposed in said substrate; a drain region of the second conductivity type disposed in said substrate near said source region; a quantum well layer of the second conductivity type disposed on said substrate between said source region and said drain region, said quantum well layer comprising a compound semiconductive material of a III-V type having a second bandgap smaller than the first bandgap; a barrier layer disposed on said quantum well layer between said source region and said drain region, said barrier layer comprising a compound semiconductive material of III-V type having a third bandgap larger than said first bandgap; first and second electrodes contacting the source and drain regions, respectively; an electrode over a major portion of the area separating the source and drain regions, the electrode comprising in juxtaposition to the barrier layer a gate layer of a compound semiconductive material of a III-V type having the first conductivity type and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein the substrate includes a first layer adjacent the quantum well layer which first layer is of the first conductivity type, a second layer of substantially intrinsic type adjacent said first layer and separated thereby from said source and drain regions, and a third layer adjacent the second layer and separated thereby from the first layer, said third layer being of the first conductivity type and having a higher dopant concentrations of said first conductivity type than said first layer.

Claim 13

A field-effect transistor comprising: a substrate of a compound semiconductive material of a III-V type having a first bandgap; a source region of a second conductivity type opposite a first conductivity type disposed in said substrate; a drain region of the second conductivity type disposed in said substrate near said source region; a quantum well layer of the second conductivity type disposed on said substrate between said source region and said drain region, said quantum well layer comprising a compound semiconductive material of a III-V type having a second bandgap smaller than the first bandgap; a barrier layer disposed on said quantum well layer between said source region and said drain region, said barrier layer comprising a compound semiconductive material of III-V type having a third bandgap larger than said first bandgap; first and second electrodes contacting the source and drain regions, respectively; an electrode over a major portion of the area separating the source and drain regions, the electrode comprising in juxtaposition to the barrier layer a gate layer of a compound semiconductive material of a III-V type having the first conductivity type and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein the substrate includes a first layer adjacent the quantum well layer which first layer is of the first conductivity type, a second layer of substantially intrinsic type adjacent said first layer and separated thereby from said source and drain regions, and a third layer adjacent the second layer and separated thereby from the first layer, said third layer being of the first conductivity type and having a higher dopant concentrations of said first conductivity type than said first layer.

Claim 14

A field-effect transistor, comprising: a substrate of an insulating material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a barrier layer of a wide bandgap semiconductive material disposed on said channel region; a gate layer of a semiconductive material of a first conductivity type disposed on said barrier layer; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped semiconductive material of said first conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of doped semiconductive material of said first conductivity type disposed on said second layer, said third layer contacting said channel region, said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.

Claim 15

A field-effect transistor, comprising: a substrate of an insulating material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a barrier layer of a wide bandgap semiconductive material disposed on said channel region; a gate layer of a semiconductive material of a first conductivity type disposed on said barrier layer; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped semiconductive material of said first conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of doped semiconductive material of said first conductivity type disposed on said second layer, said third layer contacting said channel region, said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.

Claim 16

A field-effect transistor, comprising: a substrate of a semiconductive material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a barrier layer of a wide bandgap semiconductive material disposed on said channel region; a gate layer of a semiconductive material of a first conductivity type disposed on said barrier layer; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped semiconductive material of said first conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of doped semiconductive material of said first conductivity type disposed on said second layer, said third layer contacting said channel region, said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.

Claim 17

A field-effect transistor, comprising: a substrate of a semiconductive material; a buffer layer disposed on said substrate; a channel region comprising a semiconductive material disposed on said buffer layer; a barrier layer of a wide bandgap semiconductive material disposed on said channel region; a gate layer of a semiconductive material of a first conductivity type disposed on said barrier layer; a source region of a second conductivity type opposite said first conductivity type contacting said channel region proximate a first end of said channel region; a drain region of said second conductivity type contacting said channel region proximate a second end of said channel region; ohmic contact metal regions respectively disposed on said source and drain regions; and a gate metal contact disposed on said gate layer to form an ohmic contact therewith; wherein said buffer layer includes a first layer of doped semiconductive material of said first conductivity type and disposed on said substrate, said first layer having a first dopant concentration, a second layer of undoped semiconductive material disposed on said first layer, and a third layer of doped semiconductive material of said first conductivity type disposed on said second layer, said third layer contacting said channel region, said third layer having a second dopant concentration that is less than said first dopant concentration of said first layer.