US5161160A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for testability
Assignee: Toshiba Corp
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Filing: 1990-02-01
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Granted: 1992-11-03
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Expires: 2010-02-01
Abstract
Abstract An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, includes: many scan register groups obtained by dividing many F/Fs provided in each functional block, many scan paths for scanning a plurality of test data used for input and output operations for the scan register groups, wherein a scan path is provided for each scan register group, and a decoder for designating the scan paths and controlling the input and output operations of test signals used for testing the scan register groups. A first scan register group in each functional group is composed of scan registers only used for the input operations to other functional blocks, a second scan register group is composed of scan registers only used for the output operations to other functional blocks and a third scan register group is composed of scan registers used for the input and output operations to the same functional block. Each scan path is connected to a common bus provided in the functional circuit. The common bus includes many signal lines through which the test data is transferred, and the scan path connected to a first scan register group is connected to a first pair of signal lines, the scan path connected to the second scan register group is connected to a second pair of signal lines, and the scan path connected to the third scan register group is connected to a third pair of signal lines.
Inventors
- 👤 Toshiyuki Yaguchi
- 👤 Koichi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:18
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
237 words
An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, comprising: a plurality of register groups obtained by dividing a plurality of registers provided in each functional block; a plurality of scan paths for scanning a plurality of test data used for input and output operations for the register groups, a scan path being provided for each register group: and control means for designating the scan paths and controlling the input and output operations of test signals used for testing the register groups, wherein a first register group in each functional block is composed of registers used only for the input operations to other functional blocks, a second register group is composed of registers used only for the output operations to other functional blocks and a third register group is composed of registers used for input and output operations to the same functional block, and wherein each scan path is connected to a common bus provided in the logic circuit, the common bus comprising a plurality of signal lines through which the test data is transferred, and the scan path connected to the first register group is connected to a first pair of signal lines, the scan path connected to the second register group is connected to a second pair of signal lines, and the scan path connected to the third register group is connected to a third pair of signal lines.
Claim 2
Dependent Claim
237 words
An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, comprising: a plurality of register groups obtained by dividing a plurality of registers provided in each functional block; a plurality of scan paths for scanning a plurality of test data used for input and output operations for the register groups, a scan path being provided for each register group: and control means for designating the scan paths and controlling the input and output operations of test signals used for testing the register groups, wherein a first register group in each functional block is composed of registers used only for the input operations to other functional blocks, a second register group is composed of registers used only for the output operations to other functional blocks and a third register group is composed of registers used for input and output operations to the same functional block, and wherein each scan path is connected to a common bus provided in the logic circuit, the common bus comprising a plurality of signal lines through which the test data is transferred, and the scan path connected to the first register group is connected to a first pair of signal lines, the scan path connected to the second register group is connected to a second pair of signal lines, and the scan path connected to the third register group is connected to a third pair of signal lines.
Claim 3
Dependent Claim
27 words
An evaluation facilitating circuit according to claim 1, wherein each scan path further comprises a switching means connected to the controlling means to address the scan path.
Claim 4
Dependent Claim
221 words
An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, comprising: a plurality of register groups obtained by dividing a plurality of registers provided in each functional block; a plurality of scan paths for scanning a plurality of test data used for input and output operations for the register groups, a scan path being provided for each register group; and control means for designating the scan paths and controlling the input and output operations of test signals used for testing the register groups, wherein a first register group in each functional group is composed of registers used only for the input operations to other functional blocks, a second register group is composed of registers used only for the output operations to other functional blocks and a third register group is composed of registers used for input and output operations to the same functional block, and each scan path is connected to a common bus provided in the logic circuit, the common bus comprising a plurality of signal lines through which the test data is transferred, and scan paths connected to the first register group and the second register group are connected to a same pair of signal lines, and the scan path connected to the third register group is connected to another pair of signal lines.
Claim 5
Dependent Claim
221 words
An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, comprising: a plurality of register groups obtained by dividing a plurality of registers provided in each functional block; a plurality of scan paths for scanning a plurality of test data used for input and output operations for the register groups, a scan path being provided for each register group; and control means for designating the scan paths and controlling the input and output operations of test signals used for testing the register groups, wherein a first register group in each functional group is composed of registers used only for the input operations to other functional blocks, a second register group is composed of registers used only for the output operations to other functional blocks and a third register group is composed of registers used for input and output operations to the same functional block, and each scan path is connected to a common bus provided in the logic circuit, the common bus comprising a plurality of signal lines through which the test data is transferred, and scan paths connected to the first register group and the second register group are connected to a same pair of signal lines, and the scan path connected to the third register group is connected to another pair of signal lines.
Claim 6
Dependent Claim
15 words
An evaluation facilitating circuit according to claim 3, wherein each register group comprises shift registers.
Claim 7
Dependent Claim
27 words
An evaluation facilitating circuit according to claim 3, wherein each scan path further comprises a switching means connected to the controlling means to address the scan path.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |