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Patent US5160922A successfully refreshed from Google Patents.
US5160922A
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System and method for dynamic avoidance of a simultaneous switching output limitation of a integrated circuit chip
Assignee: Hewlett Packard Development Co LP
•
Filing: 1990-06-29
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Granted: 1992-11-03
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Expires: 2010-06-29
Abstract
Abstract A system and method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip during a short, predetermined time window by dynamically arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the priority of the request signals based on the type and intended use of output signals from such elements, and the immediate state of the integrated circuit chip.
Inventors
- 👤 John DeRosa
- 👤 Lauren M. Hagstrom
- 👤 Lon S. Hilde
- 👤 Oren Wiesler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
75 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising means for arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during said short, predetermined time window, with N>0, M>0, and N≦M.
Claim 2
Independent Claim
75 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising means for arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during said short, predetermined time window, with N>0, M>0, and N≦M.
Claim 3
Dependent Claim
21 words
The system as recited in claim 1, wherein the means for arbitrating dynamically arbitrates said use of the M chip resources.
Claim 4
Dependent Claim
14 words
The system as recited in claim 2, wherein the chip resources are output pins.
Claim 5
Independent Claim
80 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising means for arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during each of the said time windows, with N>0, M>0, and N≦M.
Claim 6
Independent Claim
80 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising means for arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during each of the said time windows, with N>0, M>0, and N≦M.
Claim 7
Dependent Claim
21 words
The system as recited in claim 4, wherein the means for arbitrating independently determines N for each of said time periods.
Claim 8
Dependent Claim
21 words
The system as recited in claim 4, wherein the means for arbitrating dynamically arbitrates said use of the M chip resources.
Claim 9
Dependent Claim
14 words
The system as recited in claim 6, wherein the chip resources are output pins.
Claim 10
Independent Claim
76 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising means for arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the simultaneous switching output limit of the chip to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 11
Independent Claim
76 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising means for arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the simultaneous switching output limit of the chip to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 12
Dependent Claim
20 words
The system as recited in claim 8, wherein the means for arbitrating the request signals dynamically arbitrates said request signals.
Claim 13
Dependent Claim
43 words
The system as recited in claim 9, wherein the means for arbitrating further includes means for sending request granted signals to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the short, predetermined time window.
Claim 14
Independent Claim
96 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising means for arbitrating request signals from discrete on-chip logic elements for each of the plurality of time windows for assignment of output pins during each of the said time windows according to the simultaneous switching output limit of the chip and to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 15
Independent Claim
96 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising means for arbitrating request signals from discrete on-chip logic elements for each of the plurality of time windows for assignment of output pins during each of the said time windows according to the simultaneous switching output limit of the chip and to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 16
Dependent Claim
20 words
The system as recited in claim 11, wherein the means for arbitrating the request signals dynamically arbitrates said request signals.
Claim 17
Dependent Claim
43 words
The system as recited in claim 12, wherein the means for arbitrating further includes means for sending request granted signals to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for each of said time windows.
Claim 18
Independent Claim
132 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: arbitration means that further comprises, means for receiving from discrete on-chip logic elements request signals to use a particular number of output pins during a short, predetermined time window, means for assigning a priority to each of the requests based on type and intended use of signals for which the request signals are generated, means for arbitrating the request signals according to the priority of the request signals and the simultaneous switching output limit of the chip, and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 19
Independent Claim
132 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: arbitration means that further comprises, means for receiving from discrete on-chip logic elements request signals to use a particular number of output pins during a short, predetermined time window, means for assigning a priority to each of the requests based on type and intended use of signals for which the request signals are generated, means for arbitrating the request signals according to the priority of the request signals and the simultaneous switching output limit of the chip, and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 20
Dependent Claim
20 words
The system as recited in claim 14, wherein the means for arbitrating the request signals dynamically arbitrates said request signals.
Claim 21
Independent Claim
156 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: arbitration means which further comprises, means for receiving from discrete on-chip logic elements request signals to use the output pins during a plurality of short, predetermined time windows; means for assigning a priority to each of the request signals based on type and intended use of signals that are to be output, and the particular time window for which output is requested; means for arbitrating the request signals according to the priority of such request signals for a particular time window for which output is requested and the simultaneous switching output limit of the chip; and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time window for which output is requested.
Claim 22
Independent Claim
156 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: arbitration means which further comprises, means for receiving from discrete on-chip logic elements request signals to use the output pins during a plurality of short, predetermined time windows; means for assigning a priority to each of the request signals based on type and intended use of signals that are to be output, and the particular time window for which output is requested; means for arbitrating the request signals according to the priority of such request signals for a particular time window for which output is requested and the simultaneous switching output limit of the chip; and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time window for which output is requested.
Claim 23
Dependent Claim
19 words
The system as recited in claim 16, wherein the means for arbitrating the request signals dynamically arbitrates said requests.
Claim 24
Independent Claim
141 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: means for assigning a value to each output pin of the chip based on the output pin type; means for receiving request signals to use a particular number of output pins during a short, predetermined time window; means for assigning a priority to each of the request signals based on type and intended use of signals for which the request signals are generated; means for arbitrating the request signals according to the priority of such request signals and the simultaneous switching output limit of the chip; and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 25
Independent Claim
141 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: means for assigning a value to each output pin of the chip based on the output pin type; means for receiving request signals to use a particular number of output pins during a short, predetermined time window; means for assigning a priority to each of the request signals based on type and intended use of signals for which the request signals are generated; means for arbitrating the request signals according to the priority of such request signals and the simultaneous switching output limit of the chip; and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 26
Dependent Claim
20 words
The system as recited in claim 18, wherein the means for arbitrating the request signals dynamically arbitrates said request signals.
Claim 27
Independent Claim
177 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: means for assigning a value to each output pin of the chip based on the output pin type; and arbitration means that further comprises, means for receiving from discrete on-chip logic elements request signals for use of the output pins during a plurality of short, predetermined time windows, means for assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated, and the particular time window for which output is requested, means for arbitrating the request signals according to the priority of such request signals for a particular time window for which output is requested and the simultaneous switching output limit of the chip, and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time windows for which output is requested.
Claim 28
Independent Claim
177 words
A system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising: means for assigning a value to each output pin of the chip based on the output pin type; and arbitration means that further comprises, means for receiving from discrete on-chip logic elements request signals for use of the output pins during a plurality of short, predetermined time windows, means for assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated, and the particular time window for which output is requested, means for arbitrating the request signals according to the priority of such request signals for a particular time window for which output is requested and the simultaneous switching output limit of the chip, and means for sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time windows for which output is requested.
Claim 29
Dependent Claim
20 words
The system as recited in claim 20, wherein the means for arbitrating the request signals dynamically arbitrates said request signals.
Claim 30
Independent Claim
73 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during said short, predetermined time window, with N>0, M>0, and N≦M.
Claim 31
Independent Claim
73 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during said short, predetermined time window, with N>0, M>0, and N≦M.
Claim 32
Dependent Claim
18 words
The method as recited in claim 22, wherein arbitrating includes dynamically arbitrating said use of M chip resources.
Claim 33
Dependent Claim
15 words
The method as recited in claim 23, wherein arbitrating chip resources includes arbitrating output pins.
Claim 34
Independent Claim
78 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during each of the said time windows, with N>0, M>0, and N≦M.
Claim 35
Independent Claim
78 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising arbitrating, according to the simultaneous switching output limit of the chip, the use of M chip resources of a predetermined type of which only N of such chip resources are used during each of the said time windows, with N>0, M>0, and N≦M.
Claim 36
Dependent Claim
19 words
The method as recited in claim 25, wherein arbitrating includes independently determining N for each of said time periods.
Claim 37
Dependent Claim
18 words
The method as recited in claim 25, wherein arbitrating includes dynamically arbitrating the use of M chip resources.
Claim 38
Dependent Claim
15 words
The method as recited in claim 27, wherein arbitrating chip resources includes arbitrating output pins.
Claim 39
Independent Claim
75 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the simultaneous switching output limit of the chip and to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 40
Independent Claim
75 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during a short, predetermined time window, comprising arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the simultaneous switching output limit of the chip and to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 41
Dependent Claim
18 words
The method as recited in claim 29, wherein arbitrating the request signals includes dynamically arbitrating said request signals.
Claim 42
Dependent Claim
39 words
The method as recited in claim 30, wherein the method further includes sending request granted signals to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the short, predetermined time window.
Claim 43
Independent Claim
94 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising arbitrating request signals from discrete on-chip logic elements for each of the plurality of time windows for assignment of output pins during each of the said time windows according to the simultaneous switching output limit of the chip and to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 44
Independent Claim
94 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip at or below a predetermined limit for the chip during each of a plurality of short, predetermined time windows, comprising arbitrating request signals from discrete on-chip logic elements for each of the plurality of time windows for assignment of output pins during each of the said time windows according to the simultaneous switching output limit of the chip and to a priority of the request signals based on the type and intended use of output signals from such elements.
Claim 45
Dependent Claim
18 words
The method as recited in claim 32, wherein arbitrating the request signals includes dynamically arbitrating said request signals.
Claim 46
Dependent Claim
39 words
The method as recited in claim 33, wherein the method further includes sending request granted signals to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for each of said time windows.
Claim 47
Independent Claim
144 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising the steps of: (a) assigning a value to each output pin of the chip based on the output pin type; (b) receiving from discrete on-chip logic elements request signals to use a particular number of output pins during a short, predetermined time window; (c) assigning a priority to each of the request signals based on type and intended use of signals for which the request signals are generated; (d) arbitrating the request signals according to the priority of such request signals and the simultaneous switching output limit of the chip; and (e) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 48
Independent Claim
144 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising the steps of: (a) assigning a value to each output pin of the chip based on the output pin type; (b) receiving from discrete on-chip logic elements request signals to use a particular number of output pins during a short, predetermined time window; (c) assigning a priority to each of the request signals based on type and intended use of signals for which the request signals are generated; (d) arbitrating the request signals according to the priority of such request signals and the simultaneous switching output limit of the chip; and (e) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 49
Dependent Claim
18 words
The method as recited in claim 35, wherein the arbitrating step further includes dynamically arbitrating said request signals.
Claim 50
Independent Claim
169 words
A method system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising the steps of: (a) assigning a value to each output pin of the chip based on the output pin type; and (b) receiving from discrete on-chip logic elements request signals to use particular output pins during a plurality of short, predetermined time windows; (c) assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated, and the particular time window for which output is requested; (d) arbitrating the request signals according to the priority of such request signals for the particular time window for which output is requested and the simultaneous switching limit of the chip; and (e) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time window for which output is requested.
Claim 51
Independent Claim
169 words
A method system for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising the steps of: (a) assigning a value to each output pin of the chip based on the output pin type; and (b) receiving from discrete on-chip logic elements request signals to use particular output pins during a plurality of short, predetermined time windows; (c) assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated, and the particular time window for which output is requested; (d) arbitrating the request signals according to the priority of such request signals for the particular time window for which output is requested and the simultaneous switching limit of the chip; and (e) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time window for which output is requested.
Claim 52
Dependent Claim
18 words
The method as recited in claim 37, wherein the arbitrating step further includes dynamically arbitrating said request signals.
Claim 53
Independent Claim
126 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising the steps of: (a) receiving from discrete on-chip logic elements request signals to use a particular number of output pins during a short, predetermined time window; (b) assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated; (c) arbitrating the request signals according to the priority of such request signals and the simultaneous switching output limit of the chip; and (d) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 54
Independent Claim
126 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip, comprising the steps of: (a) receiving from discrete on-chip logic elements request signals to use a particular number of output pins during a short, predetermined time window; (b) assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated; (c) arbitrating the request signals according to the priority of such request signals and the simultaneous switching output limit of the chip; and (d) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the time window.
Claim 55
Dependent Claim
18 words
The method as recited in claim 39, wherein the arbitrating step further includes dynamically arbitrating said request signals.
Claim 56
Independent Claim
150 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit of the chip, comprising the steps of: (a) receiving from discrete on-chip logic elements request signals to use the output pins during a plurality of short, predetermined time windows; (b) assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated, and the particular time window for which output is requested; (c) arbitrating the request signals according to the priority of such request signals for the particular time window for which output is requested and the simultaneous switching limit of the chip; and (d) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time window for which output is requested.
Claim 57
Independent Claim
150 words
A method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit of the chip, comprising the steps of: (a) receiving from discrete on-chip logic elements request signals to use the output pins during a plurality of short, predetermined time windows; (b) assigning a priority to each of the request signals based on type and intended use of signals for which request signals are generated, and the particular time window for which output is requested; (c) arbitrating the request signals according to the priority of such request signals for the particular time window for which output is requested and the simultaneous switching limit of the chip; and (d) sending a request granted signal to the discrete on-chip logic elements that are selected in arbitration and granted access to output pins for the particular time window for which output is requested.
Claim 58
Dependent Claim
18 words
The method as recited in claim 41, wherein the arbitrating step further includes dynamically arbitrating said request signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |