Circuit for controlling the output of a sense amplifier

Claim 2

A circuit for controlling the output of a sense amplifier in a semiconductor memory having a sense amplifier for sensing and amplifying the data retrieved from a selected memory cell, and I/O pad and a data latch circuit connected to the I/O pad, comprising: sense amplifier output detection means for detecting the state of data pairs output from the sense amplifier; control signal generating means for receiving an address transition detection signal and the output of the sense amplifier output detection means to generate a control signal; and transfer means connected between the sense amplifier and the data latch circuit, for responding to the output of the control signal generating means; whereby the output of the control signal generating means is fed back to the sense amplifier.

Claim 3

The circuit for controlling the output of a sense amplifier as claimed in claim 1, wherein said sense amplifier output detection means produces a signal to simultaneously disable said sense amplifier and said transfer means when a pair of data outputs of the sense amplifier have different logic states.

Claim 4

The circuit for controlling the output of a sense amplifier as claimed in claim 1, wherein said sense amplifier output detection means is an exclusive NOR gate for receiving said data output pair.

Claim 5

The circuit for controlling the output of a sense amplifier as claimed in claim 1, wherein said control signal generating means is a NOR gate for receiving the output of said sense amplifier output means and the address transition detection signal.

Claim 6

The circuit for controlling the output of a sense amplifier as claimed in claim 2, wherein said sense amplifier output detection means is an exclusive NOR gate for receiving said data output pair.

Claim 7

A circuit for controlling the output of a sense amplifier, comprising: sense amplifier output detection means for providing an intermediate signal by detecting the state of data pairs from a sense amplifier; control signal generating means for receiving an address transition detection signal and the intermediate signal of the sense amplifier output detection means to generate a control signal; transfer means connected between the sense amplifier and a data latch circuit, for generating output signals in response to the control signal from the control signal generating means; and means for feeding the control signals back to the sense amplifier.

Claim 8

A circuit for controlling the output of a sense amplifier, comprising: sense amplifier output detection means for providing an intermediate signal by detecting the state of data pairs from a sense amplifier; control signal generating means for receiving an address transition detection signal and the intermediate signal of the sense amplifier output detection means to generate a control signal; transfer means connected between the sense amplifier and a data latch circuit, for generating output signals in response to the control signal from the control signal generating means; and means for feeding the control signals back to the sense amplifier.

Claim 9

The circuit for controlling the output of a sense amplifier as claimed in claim 6, further comprised of said sense amplifier output detection means generating a signal to simultaneously disable the sense amplifier and said transfer means when said data pairs have different logic states.

Claim 10

The circuit for controlling the output of a sense amplifier as claimed in claim 6, wherein said sense amplifier output detection means is an exclusive NOR gate for receiving said data output pair.

Claim 11

The circuit for controlling the output of a sense amplifier as claimed in claim 7, wherein said sense amplifier output detection means is an exclusive NOR gate for receiving said data output pair.

Claim 12

The circuit for controlling the output of a sense amplifier as claimed in claim 6, wherein said control signal generating means is a NOR gate for receiving the output of said sense amplifier output means and an address transition detection signal.

Claim 13

The circuit for controlling the output of a sense amplifier as claimed in claim 1, wherein said sense amplifier output detection means enables said sense amplifier and said transfer means whenever said state of data pairs from said sense amplifier is equal.

Claim 14

The circuit for controlling the output of a sense amplifier as claimed in claim 1, wherein said sense amplifier output detection means simultaneously disables said sense amplifier and said transfer means only when said data pairs have different states.

Claim 15

The circuit for controlling the output of a sense amplifier as claimed in claim 6, further comprised of said sense amplifier output detection means generating a signal to enable said sense amplifier and said transfer means whenever said data pairs have the same logic states.

Claim 16

The circuit for controlling the output of a sense amplifier as claimed in claim 6, further comprised of said sense amplifier output detection means generating a signal to simultaneously disable said sense amplifier and said transfer means only when said data pairs have different logic states.

Claim 17

A circuit for optimizing output signals of a sense amplifier provided in a pair of data lines, comprising: first transistor means interposed between first and second data lines and coupled to receive said output signals provided from said first and second data lines, for equalizing voltage potentials of said first and second data lines in dependence upon reception of an equalizing signal; inverter means coupled to receive said output signals, for inverting said output signals to provide first and second inverted signals for said first and second data lines; first gate means coupled to receive said first and second inverted signals, for providing an intermediate signal in dependence upon reception of said first and second inverted signals; second gate means coupled to receive said intermediate signal and an address transition detection signal, for providing a control signal in dependence upon reception of said intermediate signal and said address transition detection signal, and for feeding said control signal back to said sense amplifier for controlling generation of said output signals provided in said first and second data lines; and second transistor means coupled to receive said first and second inverted signal, for providing optimized output signals in response to said control signal.

Claim 18

A circuit for optimizing output signals of a sense amplifier provided in a pair of data lines, comprising: first transistor means interposed between first and second data lines and coupled to receive said output signals provided from said first and second data lines, for equalizing voltage potentials of said first and second data lines in dependence upon reception of an equalizing signal; inverter means coupled to receive said output signals, for inverting said output signals to provide first and second inverted signals for said first and second data lines; first gate means coupled to receive said first and second inverted signals, for providing an intermediate signal in dependence upon reception of said first and second inverted signals; second gate means coupled to receive said intermediate signal and an address transition detection signal, for providing a control signal in dependence upon reception of said intermediate signal and said address transition detection signal, and for feeding said control signal back to said sense amplifier for controlling generation of said output signals provided in said first and second data lines; and second transistor means coupled to receive said first and second inverted signal, for providing optimized output signals in response to said control signal.

Claim 19

The circuit for optimizing output signals of a sense amplifier as claimed in claim 15, wherein said first transistor means is a PMOS transistor having a gate coupled to receive said equalizing signal.

Claim 20

The circuit for optimizing output signals of a sense amplifier as claimed in claim 15, wherein said first gate means is an exclusive NOR gate and said second gate means is a NOR gate.

Claim 21

The circuit for optimizing output signals of a sense amplifier as claimed in claim 15, wherein said second transistor means comprises first and second PMOS transistors having each respective gate electrodes coupled to receive said control signal.