Information processor performing interrupt operation in two modes

Claim 1

An information processor comprising: a program memory for storing a program to be executed; a central processing unit for performing a normal program operation and an interruption operation; and at least one interface unit to be coupled to peripheral equipment for transferring data between said central processing unit and said peripheral equipment, said central processing unit including: a program counter for reading said program out of said program memory; a status word register for storing information representative of an execution condition of said central processing unit; a stack memory for saving a content of at least one of said program counter and said status word register; said interface unit including: a mode register which is brought programmably into one of a first state and a second state to produce programmably one of a first mode signal and a second mode signal; and means, coupled to said mode register and responsive to an interruption request signal supplied thereto, for generating first information when said mode register is brought into said first state to produce said first mode signal and second information when said mode register is brought into said second state to produce said second mode signal, said first information designating a first interruption which is executed after the contents of said program counter and said status word register are saved and wherein said program is resumed after completion of execution of said first interruption where the program was interrupted, and said second information designating a second interruption which is executed without the contents of said program counter and said status word register being saved and wherein said program is resumed at its point of interruption after completion of execution of said second interruption where the program was interrupted; said central processing unit further including means, responsive to said first information, for saving the contents of said program counter and said status word register and thereafter executing said first interruption and resuming said program thereafter by returning the saved contents to said program counter and said status word register, respectively, and means, responsive to said second information, for inhibiting change in the contents of said program counter and said status word register and executing said second interruption without saving the contents of said program counter and status word register and without reading any program from said program memory and resuming said program thereafter by allowing said contents of said program counter and said status word register to change.