Data transfer unit for small computer system with simultaneous transfer to two memories and error detection and rewrite to substitute address

Claim 1

A data transfer unit for a computer system forming part of a data network utilizing an SCSi bus which has a host computer, a main storage unit and an auxiliary storage unit, said data transfer unit comprising: data transfer means for transferring data between the host computer and the main and auxiliary storage units; data buffer means for temporarily storing data outputted from the host computer via the data transfer means and for outputting the data to the main and auxiliary storage units via the data transfer means; a direct memory access controller for controlling the data transfers between the data buffer means and the host computer, between the data buffer means and the main storage unit, and between the data buffer means and the auxiliary storage unit; control means for controlling the direct memory access controller, whereby said data transfer unit transfers the data outputted from the host computer from the data buffer means to both the main and auxiliary storage units simultaneously in an operation mode during which data is transferred from the host computer to the storage units and successively transfers the data for storage in a first one of said storage units which is operating normally when an error occurs in a second one of said storage units; and said transfer unit detecting an address of an error containing storage region in the second one of said storage units in which said error occurs, assigning a normal address as a substitute address for the error address, and transferring data from an address in the other storage unit corresponding to the error address to the substitute address.