Input protection circuit for CMOS devices

Claim 2

In an MOS semiconductor circuit, an input protection circuit coupled to an input pad and to other circuitry in the MOS semiconductor circuit, said MOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input node coupled to an input pad; two complementary true gated diodes, including a first true gated diode having a P-doped drain node coupled to said input node and a gate node coupled to said high voltage power supply node, and a second true gated diode having a N-doped drain node coupled to said input node and a gate node coupled to said second power supply node.

Claim 3

An input protection circuit as set forth in claim 1, wherein said true gated diodes each have an underlying vertical parasitic bipolar transistor but no underlying lateral parasitic bipolar transistor.

Claim 4

An input protection circuit as set forth in claim 1, including an input resistor, having a resistance of less than 200 ohms, coupling said input pad to said input node.

Claim 5

An input protection circuit as set forth claim 1, including an input resistor having a resistance of less than 100 ohms coupling said input pad to said input node, wherein said first and second true gated diodes are sized so as to be able to nondestructively absorb a peak electrostatic discharge current of at least 2.6 amperes.

Claim 6

In an MOS semiconductor circuit, an input protection circuit coupled to an input pad and to other circuitry in the MOS semiconductor circuit, said MOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input node coupled to an input pad; two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain node coupled to said input node, an insulated gate node coupled to said high voltage power supply node, and an N-doped source node, and (2) a second true gated diode having a N-doped drain node, an insulated gate node coupled to said second power supply node, and an P-doped source node.

Claim 7

In an MOS semiconductor circuit, an input protection circuit coupled to an input pad and to other circuitry in the MOS semiconductor circuit, said MOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input node coupled to an input pad; two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain node coupled to said input node, an insulated gate node coupled to said high voltage power supply node, and an N-doped source node, and (2) a second true gated diode having a N-doped drain node, an insulated gate node coupled to said second power supply node, and an P-doped source node.

Claim 8

An input protection circuit as set forth in claim 5, wherein said true gated diodes each have an underlying vertical parasitic bipolar transistor but no underlying lateral parasitic bipolar transistor.

Claim 9

An input protection circuit as set forth in claim 5, including an input resistor, having a resistance of less than 200 ohms, coupling said input pad to said input node.

Claim 10

An input protection circuit as set forth in claim 5, including an input resistor having a resistance of less than 100 ohms coupling said input pad to said input node, wherein said first and second true gated diodes are sized so as to be able to nondestructively absorb a peak electrostatic discharge current of at least 2.6 amperes.

Claim 11

In an MOS semiconductor circuit, an input protection circuit coupled to an input pad and to other circuitry in the MOS semiconductor circuit, said MOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input node coupled to an input pad; two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain region, an insulated gate node coupled to said high voltage source node, and no source region, and (2) a second true gated diode having a N-doped drain region, an insulated gate node coupled to said second power supply node and no source region.

Claim 12

In an MOS semiconductor circuit, an input protection circuit coupled to an input pad and to other circuitry in the MOS semiconductor circuit, said MOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input node coupled to an input pad; two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain region, an insulated gate node coupled to said high voltage source node, and no source region, and (2) a second true gated diode having a N-doped drain region, an insulated gate node coupled to said second power supply node and no source region.

Claim 13

An input protection circuit as set forth in claim 9, wherein said true gated diodes each have an underlying vertical parasitic bipolar transistor but no underlying lateral parasitic bipolar transistor.

Claim 14

An input protection circuit as set forth in claim 9, including an input resistor, having a resistance of less than 200 ohms, coupling said input pad to said input node.

Claim 15

An input protection circuit as set forth claim 9, including an input resistor having a resistance of less than 100 ohms coupling said input pad to said input node, wherein said first and second true gated diodes are sized so as to be able to nondestructively absorb a peak electrostatic discharge current of at least 2.6 amperes.

Claim 16

An input protection circuit formed along the periphery of a CMOS semiconductor circuit, coupling an input pad to circuitry in the interior portion of the CMOS semiconductor circuit, said CMOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input connector, having a resistance of less than 20 ohms, coupling an input pad to an input node; and two complementary true gated diodes, including a first true gated diodes having a P-doped drain node coupled to said input node and a gate node coupled to said high voltage power supply node, and a second true gated diode having a N-doped drain node coupled to said input node and a gate node coupled to said second power supply node.

Claim 17

An input protection circuit formed along the periphery of a CMOS semiconductor circuit, coupling an input pad to circuitry in the interior portion of the CMOS semiconductor circuit, said CMOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input connector, having a resistance of less than 20 ohms, coupling an input pad to an input node; and two complementary true gated diodes, including a first true gated diodes having a P-doped drain node coupled to said input node and a gate node coupled to said high voltage power supply node, and a second true gated diode having a N-doped drain node coupled to said input node and a gate node coupled to said second power supply node.

Claim 18

An input protection circuit as set forth in claim 13, wherein said true gated diodes each have an underlying vertical parasitic bipolar transistor but no underlying lateral parasitic bipolar transistor.

Claim 19

An input protection circuit formed along the periphery of a CMOS semiconductor circuit, coupling an input pad to circuitry in the interior portion of the CMOS semiconductor circuit, said CMOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input connector, having a resistance of less than 20 ohms, coupling an input pad to an input node; and two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain region, an insulated gate node coupled to said high voltage power supply node, and an N-doped source region, and (2) a second true gated diode having a N-doped drain region, an insulated gate node coupled to said second power supply node, and an P-doped source region.

Claim 20

An input protection circuit formed along the periphery of a CMOS semiconductor circuit, coupling an input pad to circuitry in the interior portion of the CMOS semiconductor circuit, said CMOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input connector, having a resistance of less than 20 ohms, coupling an input pad to an input node; and two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain region, an insulated gate node coupled to said high voltage power supply node, and an N-doped source region, and (2) a second true gated diode having a N-doped drain region, an insulated gate node coupled to said second power supply node, and an P-doped source region.

Claim 21

An input protection circuit as set forth in claim 15, wherein said true gated diodes each have an underlying vertical parasitic bipolar transistor but no underlying lateral parasitic bipolar transistor.

Claim 22

An input protection circuit formed along the periphery of a CMOS semiconductor circuit, coupling an input pad to circuitry in the interior portion of the CMOS semiconductor circuit, said CMOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input connector, having a resistance of less than 20 ohms, coupling an input pad to an input node; and two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain region, an insulated gate node coupled to said high voltage power supply node, and no source region, and said second true gated diode having a N-doped drain region, an insulated gate node coupled to said second power supply node, and no source region.

Claim 23

An input protection circuit formed along the periphery of a CMOS semiconductor circuit, coupling an input pad to circuitry in the interior portion of the CMOS semiconductor circuit, said CMOS semiconductor circuit including a high voltage source node and a low voltage source node; said input protection circuit comprising: an input connector, having a resistance of less than 20 ohms, coupling an input pad to an input node; and two complementary true gated diodes, including (1) a first true gated diode having a P-doped drain region, an insulated gate node coupled to said high voltage power supply node, and no source region, and said second true gated diode having a N-doped drain region, an insulated gate node coupled to said second power supply node, and no source region.

Claim 24

An input protection circuit as set forth in claim 17, wherein said true gated diodes each have an underlying vertical parasitic bipolar transistor but no underlying lateral parasitic bipolar transistor.