Digital information coding system which evenly distributes valid input data to digital signal processors operating in parallel

Claim 1

A digital signal processing apparatus comprising memory means which stores digital signal input information which is to be processed and reads out the stored information; a task controller which determines the total quantity of valid information which is contained in the digital information to be processed and produces address control signals for dividing the information to be processed into a plurality of assigned divisions so that each of said plurality of assigned divisions contains substantially the same individual quantity of valid information out of said total quantity of valid information; and a plurality of digital signal processors which receive and are responsive to said address control signals from said task controller to adjust the addresses of said assigned divisions of said information which is to be processed so that each of said assigned divisions is directed to a separate one of said digital signal processors, which read information out of said memory means to implement coding processes, and which output the results of the digital signal processes performed thereby.