US5155831A
Expired / Lapsed
US
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Data processing system with fast queue store interposed between store-through caches and a main memory
Assignee: International Business Machines Corp
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Filing: 1989-04-24
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Granted: 1992-10-13
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Expires: 2009-04-24
Abstract
Abstract A fast queue mechanism is provided which keeps a queue of changes (i.e. store actions) issued by each processor, which queue is accessible by all processors. When any processor issues a store action to a line of memory in the queue, the old data is overwritten with the new data. If the queue does not currently have a corresponding entry, a new entry is activated. Room for the new entry is made by selecting some existing entry, either the oldest or the least recently used, to be removed. An entry that is to be removed is first used to update the line corresponding to it in main memory. After the changes held in the entry to be removed are applied to the old value of the line (from main memory) and the updated value is put back into main memory, the entry in the queue is removed by marking it "empty". When a processor accesses a line of data not in its cache, a cache miss occurs and it is necessary to fetch the line from main memory. Such fetches are monitored by the queue mechanism to see if it is holding changes to the line being fetched. If so, the changes are applied to the line coming from main memory before the line is sent to the requesting processor. After a new entry is made in the queue mechanism, other store actions to the same entry by any processor may occur and usually a number of store actions will occur to the entry before it is removed to make room for another.
Inventors
- 👤 Philip G. Emma
- 👤 Joshua W. Knight
- 👤 James H. Pomerene
- 👤 Rudolph N. Rechtschaffen
- 👤 Frank J. Sparacio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:15
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0828
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
294 words
In a data processing apparatus which includes a main memory and a plurality of processor units, each with store through cache memory means, the combination comprising: queue memory means interposed between said main memory and said processor units, with storage positions for storing a limited number of data units intended for storage in main memory; comparison means coupled to said queue memory means and responsive to a newly received data unit to be stored at an address in main memory, which data unit may be received from any said processor unit, for indicating a presence of a data unit stored in said queue memory means which has a matching address; means coupled to such queue memory means and responsive to said presence indication for modifying said stored data unit in said queue memory means to correspond to said newly received data unit; means coupled to said queue memory means and responsive to no matching being found between the address of said newly received data unit and the addresses of data units stored in said queue memory means, to store said newly received data unit in said queue memory means; means coupled to said comparison means for intercepting a fetch command to an address in main memory, said fetch command issued in response to a cache miss, and for providing said address in main memory to said comparison means; read-out means responsive to a match indication between sad main memory address and an address in said queue memory means for reading out to a processor unit which issued said fetch command, a data unit in conformance with the data unit in said queue memory means at said matching address; and means for periodically transferring data unit from said queue memory means to said main memory.
Claim 2
Dependent Claim
294 words
In a data processing apparatus which includes a main memory and a plurality of processor units, each with store through cache memory means, the combination comprising: queue memory means interposed between said main memory and said processor units, with storage positions for storing a limited number of data units intended for storage in main memory; comparison means coupled to said queue memory means and responsive to a newly received data unit to be stored at an address in main memory, which data unit may be received from any said processor unit, for indicating a presence of a data unit stored in said queue memory means which has a matching address; means coupled to such queue memory means and responsive to said presence indication for modifying said stored data unit in said queue memory means to correspond to said newly received data unit; means coupled to said queue memory means and responsive to no matching being found between the address of said newly received data unit and the addresses of data units stored in said queue memory means, to store said newly received data unit in said queue memory means; means coupled to said comparison means for intercepting a fetch command to an address in main memory, said fetch command issued in response to a cache miss, and for providing said address in main memory to said comparison means; read-out means responsive to a match indication between sad main memory address and an address in said queue memory means for reading out to a processor unit which issued said fetch command, a data unit in conformance with the data unit in said queue memory means at said matching address; and means for periodically transferring data unit from said queue memory means to said main memory.
Claim 3
Dependent Claim
54 words
The invention as defined in claim 1 wherein said transferring means further comprises: means for removing data units stored in said queue memory means based upon predetermined criteria, and storing said removed data units at addresses in main memory which correspond to the addresses of said removed data units in said queue memory means.
Claim 4
Dependent Claim
29 words
The invention as defined in claim 2 further comprising: status means for evidencing an active or empty state of each data unit storage position in said queue memory means.
Claim 5
Dependent Claim
40 words
The invention as defined in claim 3 further comprising: means for altering said status means for a data unit storage position from which data is removed and stored in main memory by indicating an empty state for said storage position.
Claim 6
Dependent Claim
40 words
The invention as defined in claim 1 further comprising: means responsive to a no-match indication for causing the data unit for which said fetch command was issued to be accessed from main memory and transferred to said requesting processor unit.
Claim 7
Dependent Claim
60 words
The invention as defined in claim 1 wherein said read-out means comprises: register means for receiving a data unit from said main memory at said indicated address; means for overwriting said received data unit with the data unit in said queue memory means having a matching address; and means for transmitting said overwritten data unit to said requesting processor unit.
Claim 8
Dependent Claim
19 words
The invention as defined in claim 6 further comprising: means for updating main memory with said overwritten data unit.
Claim 9
Dependent Claim
29 words
The invention as defined in claim 7 further comprising: status means for evidencing an active or empty state of each data unit storage position in said queue memory means.
Claim 10
Dependent Claim
39 words
The invention as defined in claim 8 further comprising: means for altering said status means to evidence an empty storage position in said queue memory means when data in that storage position is removed and stored in main memory.
Claim 11
Dependent Claim
265 words
In a data processing apparatus which includes a main memory and a plurality central processor with associated store-through cache memories, a fast queue mechanism interposed between said central processors and said main memory, said fast queue mechanism comprising: a queue memory having a plurality of lines of data storage, each line capable of storing a plurality of byte entries, each byte entry having a specific address; a line address memory for storing the address of entries in said queue memory; means for receiving a new entry and its associated address to be stored in said main memory from one of said central processor units; a compare circuit connected to said line address memory for determining if the address of said new entry matches a stored address in said line address memory, and generating a match signal if a match if found or a no-match signal if no match is found; circuit means responsive to a no-match signal for storing said new entry in a line of said queue memory and updating said line address memory accordingly, and further responsive to a match signal to alter the entry corresponding to said stored address to conform with said new entry; means for monitoring a fetch command to main memory, issued by a central processor in response to a cache-miss, and responsive to a determination by said compare circuit that data having an identical address to the data being fetched is present in said queue memory, to modify said fetched data from main memory to make said fetched data conform to the data stored in said queue memory.
Claim 12
Dependent Claim
265 words
In a data processing apparatus which includes a main memory and a plurality central processor with associated store-through cache memories, a fast queue mechanism interposed between said central processors and said main memory, said fast queue mechanism comprising: a queue memory having a plurality of lines of data storage, each line capable of storing a plurality of byte entries, each byte entry having a specific address; a line address memory for storing the address of entries in said queue memory; means for receiving a new entry and its associated address to be stored in said main memory from one of said central processor units; a compare circuit connected to said line address memory for determining if the address of said new entry matches a stored address in said line address memory, and generating a match signal if a match if found or a no-match signal if no match is found; circuit means responsive to a no-match signal for storing said new entry in a line of said queue memory and updating said line address memory accordingly, and further responsive to a match signal to alter the entry corresponding to said stored address to conform with said new entry; means for monitoring a fetch command to main memory, issued by a central processor in response to a cache-miss, and responsive to a determination by said compare circuit that data having an identical address to the data being fetched is present in said queue memory, to modify said fetched data from main memory to make said fetched data conform to the data stored in said queue memory.
Claim 13
Dependent Claim
70 words
The invention as recited in claim 10 further comprising: update circuit means for removing data from a line of storage in said queue memory, altering said line address memory and causing said removed data to be stored in main memory, said update circuit means operating in accordance with predetermined criteria relating to the status of use of the removed data in comparison with other data stored in said queue memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |