Arrangement for testing digital circuit devices having bidirectional outputs

Claim 1

1. An arrangement for testing the inputs and outputs of a digital circuit device, said digital circuit device including a plurality of inputs and outputs arranged in sequential groups, and a test mode control input for activating said arrangement, said arrangement comprising: a first test signal input circuit connected to the first input of said sequential group, said first test signal input circuit arranged to receive a test signal applied to said first input and to pass said test signal to said first sequential group input, and to an included test out lead; a second test signal input circuit including gate means having a first input lead connected to a test out lead, and a second input lead connected to the next input of said sequential group, said gate means arranged to exclusively combine the test signal received on said second input with the test signal received on said first input and to generate and output a test out signal from an included test out lead; a first test signal output circuit including a first input connected to an output of said sequential group that is not the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said test out signal, an enable test control lead for selecting between said first and second inputs, a standard output lead for passing the signal selected, and a test out lead connected to said second input inverted signal for passing said inverted test signal to the next test circuit; a second test signal output circuit including a first input connected to an output of said sequential group that is the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said input test out signal, an enable test control lead for selecting between said first and said second inputs, and a standard output lead for passing the signal selected for input; and a test signal bidirectional output circuit including a first input connected to an output of said sequential group that is not the last output of said sequential group, a second input connected to a test out signal from an adjacent test out lead, said second input lead including means for inverting said test out signal, an enable test control lead for selecting between said first and second inputs, gate means having an output and a first input connected to said enable test control lead and a second input connected to a driver control input from said digital circuit device, a tri-state gate having an output, an input connected to an output lead of said test signal bidirectional output circuit and an enabling input connected to said gate means output, and a bidirectional input lead connected between said tri-state gate output and the bidirectional input of said digital circuit device, said gate means enabling said tri-state gate to pass said input signal selected, and alternatively, disabling said tri-state gate to pass input signals to said digital circuit device bidirectional input, said test signal bidirectional output circuit further including a test out lead connected to said bidirectional input lead for passing said test signal to the next test circuit, whereby said test signal input into said first test signal input circuit is output at said test signal bidirectional output circuit.