Patent US5155386A successfully refreshed from Google Patents.
US5155386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable hysteresis comparator
Assignee: NXP USA Inc
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Filing: 1991-06-03
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Granted: 1992-10-13
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Expires: 2011-06-03
Abstract
Abstract A comparator having programmable hysteresis is provided. The signal supplied to an inverting input of the comparator (18) is determined by the logic state of the output of comparator and is a programmable factor of one of two predetermined signals (V REF1 or V REF2 ). The programmable factor is determined by the logic states of a plurality of control signals and can be adjusted by varying the logic states of the plurality of control signals.
Inventors
- 👤 Behrooz Abdi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:29
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/086; H03K3/00; H03K3/02; H03K3/023; H03K3/0233; H03K3/02337
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
172 words
A comparator circuit having programmable hysteresis, comprising: a multiplexer having first, second and select inputs and an output, said first input being coupled to receive a first reference signal, and said second input being coupled to receive a second reference signal; a multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input being coupled to said output of said multiplexer, said plurality of control inputs being respectively coupled to receive a plurality of control signals for determining a gain factor of said multiplier-digital-to analog converter, said gain factor of said multiplier-digital-to-analog converter being utilized to program the level of said output of said multiplexer; and a comparator having first and second inputs and an output, said first input of said comparator being coupled to receive an input signal, said second input of said comparator being coupled to said output of said multiplier-digital-to-analog converter, said output of said comparator being coupled to said select input of said multiplexer and to an output of the comparator circuit.
Claim 2
Dependent Claim
172 words
A comparator circuit having programmable hysteresis, comprising: a multiplexer having first, second and select inputs and an output, said first input being coupled to receive a first reference signal, and said second input being coupled to receive a second reference signal; a multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input being coupled to said output of said multiplexer, said plurality of control inputs being respectively coupled to receive a plurality of control signals for determining a gain factor of said multiplier-digital-to analog converter, said gain factor of said multiplier-digital-to-analog converter being utilized to program the level of said output of said multiplexer; and a comparator having first and second inputs and an output, said first input of said comparator being coupled to receive an input signal, said second input of said comparator being coupled to said output of said multiplier-digital-to-analog converter, said output of said comparator being coupled to said select input of said multiplexer and to an output of the comparator circuit.
Claim 3
Dependent Claim
253 words
A comparator circuit having programmable hysteresis, comprising: a first multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input being coupled to receive a first reference signal, said plurality of control inputs being respectively coupled to receive a first plurality of control signals for determining a gain factor of said first multiplier-digital-to analog converter; a second multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input of said second multiplier-digital-to-analog converter being coupled to receive a second reference signal, said plurality of control inputs of said second multiplier-digital-to-analog converter being respectively coupled to receive a second plurality of control signals for determining a gain factor of said second multiplier-digital-to analog converter, said gain factor of said first and second multiplier-digital-to-analog converter being utilized to respectively program the level of said first and second reference signals; a multiplexer having first, second and select inputs and an output, said first input of said multiplexer being coupled to said output of said first multiplier-digital-to-analog converter, and said second input of said multiplexer being coupled to said output of said second multiplier-digital-to-analog converter; and a comparator having first and second inputs and an output, said first input of said comparator being coupled to receive an input signal, said second input of said comparator being coupled to said output of said multiplexer, said output of said comparator being coupled to said select input of said multiplexer and to an output of the comparator circuit.
Claim 4
Dependent Claim
253 words
A comparator circuit having programmable hysteresis, comprising: a first multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input being coupled to receive a first reference signal, said plurality of control inputs being respectively coupled to receive a first plurality of control signals for determining a gain factor of said first multiplier-digital-to analog converter; a second multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input of said second multiplier-digital-to-analog converter being coupled to receive a second reference signal, said plurality of control inputs of said second multiplier-digital-to-analog converter being respectively coupled to receive a second plurality of control signals for determining a gain factor of said second multiplier-digital-to analog converter, said gain factor of said first and second multiplier-digital-to-analog converter being utilized to respectively program the level of said first and second reference signals; a multiplexer having first, second and select inputs and an output, said first input of said multiplexer being coupled to said output of said first multiplier-digital-to-analog converter, and said second input of said multiplexer being coupled to said output of said second multiplier-digital-to-analog converter; and a comparator having first and second inputs and an output, said first input of said comparator being coupled to receive an input signal, said second input of said comparator being coupled to said output of said multiplexer, said output of said comparator being coupled to said select input of said multiplexer and to an output of the comparator circuit.
Claim 5
Dependent Claim
175 words
A fully differential comparator circuit having programmable hysteresis, comprising: a differential multiplexer having first, second and select inputs and an output, said first input being coupled to receive a first differential signal, and said second input being coupled to receive a second differential signal; a differential multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input being coupled to said output of said differential multiplexer, said plurality of control inputs being respectively coupled to receive a plurality of control signals for determining a gain factor of said differential multiplier-digital-to analog converter, said gain factor of said differential multiplier-digital-to-analog converter being utilized to program the level of said output of said differential multiplexer; and a comparator responsive to a differential input signal and a differential signal appearing at said output of said differential multiplier-digital-to-analog converter for providing a differential output signal, said differential output signal of said comparator being provided to said select input of said differential multiplexer and to a differential output of the fully differential comparator circuit.
Claim 6
Dependent Claim
175 words
A fully differential comparator circuit having programmable hysteresis, comprising: a differential multiplexer having first, second and select inputs and an output, said first input being coupled to receive a first differential signal, and said second input being coupled to receive a second differential signal; a differential multiplier-digital-to-analog converter having a plurality of control inputs, a reference input and an output, said reference input being coupled to said output of said differential multiplexer, said plurality of control inputs being respectively coupled to receive a plurality of control signals for determining a gain factor of said differential multiplier-digital-to analog converter, said gain factor of said differential multiplier-digital-to-analog converter being utilized to program the level of said output of said differential multiplexer; and a comparator responsive to a differential input signal and a differential signal appearing at said output of said differential multiplier-digital-to-analog converter for providing a differential output signal, said differential output signal of said comparator being provided to said select input of said differential multiplexer and to a differential output of the fully differential comparator circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |