Patent US5155385A successfully refreshed from Google Patents.
US5155385A
Expired / Lapsed
US
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Semiconductor integrated circuit device having a bias supply current
Assignee: Fujitsu VLSI Ltd
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Filing: 1991-02-21
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Granted: 1992-10-13
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Expires: 2011-02-21
Abstract
Abstract A semiconductor integrated circuit device includes a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage. A field transistor has its gate connected to receive the gate voltage from the operational amplifier and its drain connected to a resistor and to an noninverting input terminal of the operational amplifer. A field effect transistor has its gate connected to receive the gate voltage from the operational amplifier to produce a current corresponding to the input voltage. One group of current source is responsive to an output voltage of the bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit is responsive to an input digital value to selectively output the currents from the group of current sources to its common output.
Inventors
- 👤 Kunihiko Gotoh
- 👤 Yuuji Sekido
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:00
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0602; H03M1/0604; H03M1/66; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262; H03M1/74; H03M1/662; H03M1/742
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
125 words
A semiconductor integrated circuit device formed on a single semiconductor chip comprising: a bias generating circuit having a producing means for producing a gate voltage, said bias generating circuit including a plurality of field effect transistors having gates connected to receive the gate voltage from said producing means, each field effect transistor producing a respective first current; and a plurality of D/A converters, each D/A converter including at least one group of current sources responsive to said first current produced from one of said plurality of said field effect transistors to produce a plurality of second currents; and at least one switching circuit responsive to an input digital value to selectively output the second currents from said group of current sources to a common output.
Claim 2
Dependent Claim
125 words
A semiconductor integrated circuit device formed on a single semiconductor chip comprising: a bias generating circuit having a producing means for producing a gate voltage, said bias generating circuit including a plurality of field effect transistors having gates connected to receive the gate voltage from said producing means, each field effect transistor producing a respective first current; and a plurality of D/A converters, each D/A converter including at least one group of current sources responsive to said first current produced from one of said plurality of said field effect transistors to produce a plurality of second currents; and at least one switching circuit responsive to an input digital value to selectively output the second currents from said group of current sources to a common output.
Claim 3
Dependent Claim
28 words
The semiconductor integrated circuit device according to claim 1, in which said common output of said switching circuit is connected to a resistor to convert current to voltage.
Claim 4
Dependent Claim
22 words
The semiconductor integrated circuit device according to claim 1, in which said bias generating circuit is formed on said single semiconductor chip.
Claim 5
Dependent Claim
61 words
The semiconductor integrated circuit device according to claim 1, in which said switching circuit has as many switches as there are current sources in said current source group, each of said switches forming a pair with a respective one of said current sources and a number of pairs being smaller by one than a maximum value of said input digital value.
Claim 6
Dependent Claim
28 words
The semiconductor integrated circuit device according to claim 4, in which, in said switching circuit, switches corresponding in number to the input digital value are turned on simultaneously.
Claim 7
Dependent Claim
35 words
The semiconductor integrated circuit device according to claim 1, in which the input digital data are ON signals obtained by decoding input data of plural bits and correspond in number to the input digital data.
Claim 8
Dependent Claim
40 words
The semiconductor integrated circuit device according to claim 6, in which, when the input digital data has l bits, a number of said switches and a number of said current sources each equal l th power of 2 minus 1.
Claim 9
Dependent Claim
81 words
The semiconductor integrated circuit device according to claim 1, wherein said producing means comprises an operational amplifier connected to receive an input voltage at an inverting input terminal and said plurality of field effect transistors produce said first current corresponding to the input voltage and further comprising a second field effect transistor having a gate connected to the gate voltage from said operational amplifier and a drain connected to a resistor and to a non-inverting input terminal of said operational amplifier.
Claim 10
Dependent Claim
29 words
The semiconductor integrated circuit device according to claim 8, wherein said second field effect transistor and the plurality of field effect transistors have sources connected to a power supply.
Claim 11
Dependent Claim
30 words
The semiconductor integrated circuit device according to claim 8, wherein said bias generating circuit, said group of current sources and said switching circuit are formed on said single semiconductor chip.
Claim 12
Dependent Claim
33 words
The semiconductor integrated circuit device according to claim 10, wherein said second field effect transistor and said plurality of field effect transistors are formed close to each other on said single semiconductor chip.
Claim 13
Dependent Claim
44 words
The semiconductor integrated circuit device according to claim 1, further comprising data conversion means responsive to digital data to produce a select signal, and load resistors connected to outputs of said group of current sources, wherein digital data are converted to an analog voltage.
Claim 14
Dependent Claim
169 words
A semiconductor integrated circuit device, formed in a semiconductor chip, comprising: a plurality of digital to analog converters, each including an output terminal outputting an analog signal, a plurality of current source transistors having gates connected to each other, a plurality of switching transistors responsive to a digital signal and connected between the current source transistors and the output terminal, a first transistor composing a first current mirror circuit with the current source transistors, and a second current mirror circuit having a first node, connected to the first transistor, and a second node; and a current bias generating circuit including a plurality of second transistors, each second transistor connected to the second node of a respective second current mirror circuit, each having a gate, and a bias voltage generating circuit commonly supplying a bias voltage to the gate of each second transistor and including a third transistor having a gate connected to the gate of each second transistor, wherein each second transistor is arranged adjacent to the third transistor.
Claim 15
Dependent Claim
169 words
A semiconductor integrated circuit device, formed in a semiconductor chip, comprising: a plurality of digital to analog converters, each including an output terminal outputting an analog signal, a plurality of current source transistors having gates connected to each other, a plurality of switching transistors responsive to a digital signal and connected between the current source transistors and the output terminal, a first transistor composing a first current mirror circuit with the current source transistors, and a second current mirror circuit having a first node, connected to the first transistor, and a second node; and a current bias generating circuit including a plurality of second transistors, each second transistor connected to the second node of a respective second current mirror circuit, each having a gate, and a bias voltage generating circuit commonly supplying a bias voltage to the gate of each second transistor and including a third transistor having a gate connected to the gate of each second transistor, wherein each second transistor is arranged adjacent to the third transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |