US5155055A
Expired / Lapsed
US
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Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel
Assignee: Texas Instruments Inc
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Filing: 1991-04-15
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Granted: 1992-10-13
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Expires: 2011-04-15
Abstract
Abstract An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.
Inventors
- 👤 Manzur Gill
- 👤 Sung-Wei Lin
- 👤 C. Rinn Cleavelin
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:10
CPC Classifications
H; H10; H10B; H10B41/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
331 words
A method of making an array of rows and columns of nonvolatile memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of: forming a plurality of first insulator regions at said face, said first insulator regions being laterally spaced and elongate in a column direction, each first insulation region having a lateral margin that is sloped with respect to said face; forming a pair of bitlines between each pair of adjacent first insulator regions at said face, said bitlines being elongate in the column direction and of a second conductivity type opposite said first conductivity type, each bitline including a plurality of source/drain regions, each memory cell including a first source/drain region in a first bitline of said pair of bitlines, a second source/drain region in a second bitline of said pair of bitlines, and a channel in said face separating said first and second source/drain regions; forming a second insulator region on each of said first bitlines, each second insulator region having a lateral margin which is sloped with respect to said face, said lateral margins of said second insulator regions being substantially parallel to said said lateral margins of said first insulator regions, for each column of cells a junction of the sloped lateral margin of one of said second insulator regions and the sloped lateral margin of one of a pair of first insulator regions forming an insulator transition area on said face, at least a portion of said insulator transition area adjoining the first source/drain regions of cells in said column of cells; forming an insulator layer over the channel of each cell; removing insulator material in said insulator transition area above the first source/drain region in each cell to expose a portion of said semiconductor layer; and forming a tunnel window insulator on said exposed portion of said semiconductor layer for each cell, the thickness of said tunnel window being less than the thickness of said insulator layer.
Claim 2
Independent Claim
331 words
A method of making an array of rows and columns of nonvolatile memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of: forming a plurality of first insulator regions at said face, said first insulator regions being laterally spaced and elongate in a column direction, each first insulation region having a lateral margin that is sloped with respect to said face; forming a pair of bitlines between each pair of adjacent first insulator regions at said face, said bitlines being elongate in the column direction and of a second conductivity type opposite said first conductivity type, each bitline including a plurality of source/drain regions, each memory cell including a first source/drain region in a first bitline of said pair of bitlines, a second source/drain region in a second bitline of said pair of bitlines, and a channel in said face separating said first and second source/drain regions; forming a second insulator region on each of said first bitlines, each second insulator region having a lateral margin which is sloped with respect to said face, said lateral margins of said second insulator regions being substantially parallel to said said lateral margins of said first insulator regions, for each column of cells a junction of the sloped lateral margin of one of said second insulator regions and the sloped lateral margin of one of a pair of first insulator regions forming an insulator transition area on said face, at least a portion of said insulator transition area adjoining the first source/drain regions of cells in said column of cells; forming an insulator layer over the channel of each cell; removing insulator material in said insulator transition area above the first source/drain region in each cell to expose a portion of said semiconductor layer; and forming a tunnel window insulator on said exposed portion of said semiconductor layer for each cell, the thickness of said tunnel window being less than the thickness of said insulator layer.
Claim 3
Dependent Claim
59 words
The method of claim 1, further including the steps of: forming a floating gate for each memory cell, each floating gate extending over the first source/drain region, the tunnel window insulator, and a portion of the channel of a respective memory cell, and extending over a least a portion of a first insulator region adjacent said first source/drain region.
Claim 4
Dependent Claim
44 words
The method of claim 2, in which the step of forming a floating gate for each memory cell includes applying a first conductive layer over said face, patterning said first conductive layer to form spaced apart floating gate strips elongated in the column direction.
Claim 5
Dependent Claim
49 words
The method of claim 3, further comprising the steps of applying a second conductive layer over said face insulated from said floating gate strips and patterning said second conductive layer to define a plurality of wordlines, each wordline extending over the floating gates in a row of memory cells.
Claim 6
Dependent Claim
53 words
The method of claim 4, in which the step of forming a floating gate for each memory cell includes etching the floating gate strips while patterning said second conductive layer to define said wordlines so that edges of each floating gate in a row direction are aligned with respective edges of a wordline.
Claim 7
Dependent Claim
64 words
The method of claim 1, in which the step of forming first insulator regions includes applying a layer of oxidation-resistant material to said face, patterning said layer of oxidation-resistant material to leave oxidation-resistant material over channel and bitline areas of said face while exposing areas at said face where said first insulator regions will be formed, and growing field oxide in said exposed areas.
Claim 8
Dependent Claim
31 words
The method of claim 6, further including the step of forming a heavily doped channels top of the first conductivity type in said exposed areas prior to growing said field oxide.
Claim 9
Dependent Claim
19 words
The method of claim 1, in which the step of forming bitlines includes implanting an impurity into said face.
Claim 10
Dependent Claim
32 words
The method of claim 1, in which the step of forming a second insulator region on each of said first bitlines includes growing thermal oxide of a first thickness over said bitlines.
Claim 11
Dependent Claim
36 words
The method of claim 9, in which the step of forming a thin insulator transition area includes growing thermal oxide of a second thickness over said face, said first thickness being greater than said second thickness.
Claim 12
Dependent Claim
18 words
The method of claim 1, in which the step of removing insulator material includes etching the insulator material.
Claim 13
Dependent Claim
24 words
The method of claim 11, in which the width of said exposed portion is controlled by varying the length of time for the etching.
Claim 14
Dependent Claim
21 words
The method of claim 1, further comprising the step of forming a third insulator region on each of said second bitlines.
Claim 15
Independent Claim
248 words
A method of making a nonvolatile memory cell at a face of a semiconductor body having a first conductivity type, comprising the steps of: forming a first insulator region at said face, said first insulator region having a lateral margin that is sloped with respect to said face; forming first and second source/drain regions at said face, said first and second source/drain regions being of a second conductivity type opposite said first conductivity type, said first source/drain region being located adjacent said first insulator region, said second source/drain region being separated from said first source/drain region by a channel in said face; forming a second insulator region on said first source/drain region, said second insulator region having a lateral margin that is sloped with respect to said face, said lateral margin of said second insulator region being substantially parallel to said said lateral margin of said first insulator region, a junction of said sloped lateral margin of said first insulator region and said sloped lateral margin of said second insulator region forming a transition area, at least a portion of said transition area adjoining said first source/drain region; forming an insulator layer over said channel; removing insulator material in said transition area above the first source/drain region in each cell to expose a portion of said semiconductor layer; and forming a tunnel window insulator on said exposed portion of said semiconductor layer, the thickness of said tunnel window insulator being less than the thickness of said insulator layer.
Claim 16
Independent Claim
248 words
A method of making a nonvolatile memory cell at a face of a semiconductor body having a first conductivity type, comprising the steps of: forming a first insulator region at said face, said first insulator region having a lateral margin that is sloped with respect to said face; forming first and second source/drain regions at said face, said first and second source/drain regions being of a second conductivity type opposite said first conductivity type, said first source/drain region being located adjacent said first insulator region, said second source/drain region being separated from said first source/drain region by a channel in said face; forming a second insulator region on said first source/drain region, said second insulator region having a lateral margin that is sloped with respect to said face, said lateral margin of said second insulator region being substantially parallel to said said lateral margin of said first insulator region, a junction of said sloped lateral margin of said first insulator region and said sloped lateral margin of said second insulator region forming a transition area, at least a portion of said transition area adjoining said first source/drain region; forming an insulator layer over said channel; removing insulator material in said transition area above the first source/drain region in each cell to expose a portion of said semiconductor layer; and forming a tunnel window insulator on said exposed portion of said semiconductor layer, the thickness of said tunnel window insulator being less than the thickness of said insulator layer.
Claim 17
Dependent Claim
52 words
The method of claim 14, further comprising the step of forming a floating gate extending over the first source/drain region, the tunnel window insulator, and a portion of the channel of a respective memory cell, and extending over at least a portion of a first insulator region adjacent said first source/drain region.
Claim 18
Dependent Claim
20 words
The method of claim 15, further comprising the step of forming a control gate insulatively disposed adjacent said floating gate.
Claim 19
Dependent Claim
65 words
The method of claim 14, in which the step of forming said first insulator region includes applying a layer of oxidation-resistant material to said face, patterning said layer of oxidation-resistant material to leave oxidation-resistant material over channel and source/drain areas of said face while exposing areas at said face where said first insulator region will be formed, and growing field oxide in said exposed areas.
Claim 20
Dependent Claim
31 words
The method of claim 17, further including the step of forming a heavily doped channel stop of the first conductivity type in said exposed areas prior to growing said field oxide.
Claim 21
Dependent Claim
20 words
The method of claim 14, in which the step of forming source/drain regions includes implanting an impurity into said face.
Claim 22
Dependent Claim
33 words
The method of claim 14, in which the step of forming a second insulator region on said first source/drain region includes growing thermal oxide of a first thickness over said first source/drain region.
Claim 23
Dependent Claim
36 words
The method of claim 20, in which the step of forming a thin insulator transition area includes growing thermal oxide of a second thickness over said face, said first thickness being greater than said second thickness.
Claim 24
Dependent Claim
18 words
The method of claim 14, in which the step of removing insulator material includes etching the insulator material.
Claim 25
Dependent Claim
24 words
The method of claim 22, in which the width of said exposed portion is controlled by varying the length of time for the etching.
Claim 26
Dependent Claim
20 words
The method of claim 14, further comprising the step of forming a third insulator region on said second source/drain region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |