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Patent US5153856A successfully refreshed from Google Patents.
US5153856A
Expired / Lapsed
US
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DRAM controller
Assignee: Toshiba TEC Corp
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Filing: 1991-02-21
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Granted: 1992-10-06
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Expires: 2011-02-21
Abstract
Abstract A DRAM controller comprises an address output controller for transferring an address-designating signal to a dynamic RAM, a data output controller for transferring data to be written into and read-out from a memory region of the dynamic RAM which is designated by the address-designating signal, and a control circuit responsive to a mode-designating signal for generating various control signals corresponding to an access mode of the dynamic RAM designated by the mode-designating signal and for supplying control signals to the dynamic RAM, address output controller, and data output controller in a predetermined sequence. In the DRAM controller, the control circuit includes a signal-generating unit for generating control signals in a specific access mode which requires an access time longer than a machine cycle of a processor for generating the address-designating signal, the data to be written, and the mode-designating signal, the signal-generating means delaying generation control signals every time designation of the specific access mode by the mode-designating signal is repeated.
Inventors
- 👤 Toshiyasu Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:29
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/16; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
158 words
A DRAM controller comprising: address output means for transferring an address-designating signal to a dynamic RAM; data output means for transferring data to be written into and read-out from a memory region of the dynamic RAM which is designated by the address-designating signal; and control means responsive to a mode-designating signal for generating various control signals corresponding to an access mode of the dynamic RAM designated by the mode-designating signal, and for supplying control signals to said dynamic RAM, to said address output means, and to said data output means in a predetermined sequence; said control means including signal-generating means for generating control signals in a specific access mode which requires an access time longer than a machine cycle of a processor for generating the address-designating signal, the data to be written, and the mode-designating signal, said signal-generating means delaying generation of control signals every time designation of the specific access mode by the mode-designating signal is repeated.
Claim 2
Dependent Claim
158 words
A DRAM controller comprising: address output means for transferring an address-designating signal to a dynamic RAM; data output means for transferring data to be written into and read-out from a memory region of the dynamic RAM which is designated by the address-designating signal; and control means responsive to a mode-designating signal for generating various control signals corresponding to an access mode of the dynamic RAM designated by the mode-designating signal, and for supplying control signals to said dynamic RAM, to said address output means, and to said data output means in a predetermined sequence; said control means including signal-generating means for generating control signals in a specific access mode which requires an access time longer than a machine cycle of a processor for generating the address-designating signal, the data to be written, and the mode-designating signal, said signal-generating means delaying generation of control signals every time designation of the specific access mode by the mode-designating signal is repeated.
Claim 3
Dependent Claim
36 words
A controller according to claim 1, wherein said control means includes wait control means for setting the processor in a waiting state when a total period by which controls signals are delayed reaches a predetermined value.
Claim 4
Dependent Claim
43 words
A controller according to claim 2, wherein said signal generating means includes a plurality of signal generators for generating control signals and selecting means for selecting one of said signal generators responsive to designation of the specific access mode by the mode-designating signal.
Claim 5
Dependent Claim
54 words
A controller according to claim 3, wherein said plurality of signal generators includes a first signal generator for generating control signals, a second signal generator for generating control signals with a first predetermined delay, and a third signal generator for generating control signals with a second predetermined delay larger than said first predetermined delay.
Claim 6
Dependent Claim
23 words
A controller according to claim 4, wherein said selecting means includes sequential selection means for sequentially selecting said first to third signal generators.
Claim 7
Dependent Claim
34 words
A controller according to claim 5, wherein said wait control means includes setting means for setting said processor into a waiting state when it is detector that said third signal generator has been selected.
Claim 8
Dependent Claim
39 words
A controller according to claim 6, further comprising decoder means for decoding signals supplied as said mode-designation signal from an address strobe terminal, a read/write terminal, a read/write control terminal, and a part of address terminals of said processor.
Claim 9
Dependent Claim
15 words
A controller according to claim 1, wherein said specific access mode is a read-modify-write mode.
Claim 10
Dependent Claim
39 words
A controller according to claim 1, wherein said control means further includes second signal-generating means for generating control signal in another access mode which requires an access time equal to or shorter than the machine cycle of said processor.
References Cited (Backward Citations)
EP0109298A2
Cited
US4660180A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |