Interface for a thin display

Claim 2

A circuit for interfacing a video signal for a scanning color display to a matrix color display, comprising: three memory means controllable to store data and each receptive of one of three different color video signals for a scanning color display having pulse trains of serial color data separated by blanking periods; timing means for producing a timing signal corresponding to the blanking period for each video signal; control means receptive of the timing signal for controlling each of the memory means to prevent the storage of data during the blanking periods; means for temporarily receiving data from each of the three memory means to store the data as parallel data words; means for producing mixed color display data from the parallel data words comprising switching means for sequentially selecting data bits in a least significant bit order from each word in turn and producing an uninterrupted serial train of data bits alternately corresponding to three colors, the switching means including six switch circuits each having four output terminals; and applying means for applying the serial train of data bits to a matrix color display, the applying means including four input terminals each connected with a respective one of each of said output terminals of each respective one of said switch circuits.

Claim 3

The circuit according to claim 1; further comprising means for generating clock pulses; and wherein the video signals include a synchronizing signal; the timing means comprises means for counting clock pulses after the synchronizing signal to produce a start timing signal corresponding to the end of each blanking period; and the control means includes means receptive of the start timing signal to effect storage by the memory means after the end of the blanking period.

Claim 4

The circuit according to claim 1; wherein the means for temporarily receiving data comprises three registers for storing the color data for three different colors.

Claim 5

The circuit according to claim 3; wherein the switching means includes a ring counter for sequentially enabling the switch circuits to obtain data from the registers in a time sharing manner.

Claim 6

A circuit for interfacing a video signal for a scanning color display to a matrix color display, comprising: three memory means controllable to store data and each receptive of one of three different color video signals for a scanning color display having pulse trains of serial color data separated by blanking periods; timing means for producing a timing signal corresponding to the blanking period for each video signal; control means receptive of the timing signal for controlling each of the memory means to prevent the storage of data during the blanking periods; means for temporarily receiving data from each of the three memory means to store the data as parallel data words; means for producing mixed color display data from the parallel data words comprising switching means for sequentially selecting data bits in a least significant bit order from each word in turn and producing an uninterrupted serial train of data bits alternately corresponding to three colors, the switching means including at least two switch circuits each having a plurality of output terminals; and applying means for applying the serial train of data bits to a matrix color display, the applying means including a plurality of input terminals each connected with a respective one of said plurality of output terminals of each respective one of said switch circuits.

Claim 7

A circuit for interfacing a video signal for a scanning color display to a matrix color display, comprising: three memory means controllable to store data and each receptive of one of three different color video signals for a scanning color display having pulse trains of serial color data separated by blanking periods; timing means for producing a timing signal corresponding to the blanking period for each video signal; control means receptive of the timing signal for controlling each of the memory means to prevent the storage of data during the blanking periods; means for temporarily receiving data from each of the three memory means to store the data as parallel data words; means for producing mixed color display data from the parallel data words comprising switching means for sequentially selecting data bits in a least significant bit order from each word in turn and producing an uninterrupted serial train of data bits alternately corresponding to three colors, the switching means including at least two switch circuits each having a plurality of output terminals; and applying means for applying the serial train of data bits to a matrix color display, the applying means including a plurality of input terminals each connected with a respective one of said plurality of output terminals of each respective one of said switch circuits.

Claim 8

The circuit according to claim 5; further comprising means for generating clock pulses; and wherein the video signals include a synchronizing signal; the timing means comprises means for counting clock pulses after the synchronizing signal to produce a start timing signal corresponding to the end of each blanking period; and the control means includes means receptive of the start timing signal to effect storage by the memory means after the end of the blanking period.

Claim 9

The circuit according to claim 5; wherein the means for temporarily receiving data comprises three registers for storing the color data for three different colors.

Claim 10

The circuit according to claim 7; wherein the switching means comprises switch circuits connected to the registers; and a ring counter for sequentially enabling the switch circuits to obtain data from the registers in a time sharing manner.