Matrix type color television panel driver circuit

Claim 1

An MOS driver circuit for a matrix-type color television panel having color picture elements including a liquid crystal display material located at intersections of line and column electrodes for displaying a color picture by driving one line of picture elements at a time in a time-sharing manner comprising: (1) line and column electrode driver circuits for driving said line and column electrodes; (2) a synchronizing separation circuit for separating horizontal and vertical synchronizing signals from picture signals; (3) a color separation circuit for separating red, green and blue color signals from said picture signals; and (4) a control circuit responsive to the synchronizing signals from said synchronizing separation circuit for controlling said line and column electrode driver circuits, said control circuit including: (a) a sampling clock generator for generating a sampling clock during a predetermined scanning period, (b) a latch order pulse generator for generating a latch order pulse during a predetermined flyback period, (c) a reference analog data voltage generator for generating a reference analog data voltage, said reference analog data voltage being repeatedly generated and varying nonlinearly with time so as to correct a nonlinear relation between an input voltage representing brightness and an actual display brightness on the liquid crystal television panel during the predetermined scanning period in synchronism with the horizontal synchronizing signal from said synchronizing separation circuit, and (d) a column start pulse generator for generating a column start pulse in synchronism with the horizontal synchronizing signal, said column electrode driver circuit including: (a) an analog line memory circuit having, (i) a plurality of sampling pulse generators each for generating independently a sampling pulse for one column in synchronism with the column start pulse and the sampling clock from said control circuit, (ii) a plurality of first switching means comprising transmission gates for transmitting one line of separated color signals in synchronism with said sampling pulses, (iii) a plurality of first analog memory means comprising capacitors for storing said one line of separated color signals transmitted by said first switching means as analog values, and (iv) a plurality of first buffer amplifiers for amplifying said separated color signals stored in said first analog memory means, (b) an analog latch circuit having, (i) a plurality of second switching means comprising transmission gates for transmitting said one line of separated color signals stored in said first analog memory means after being amplified by said first buffer amplifiers in synchronism with said latch order pulse from said control circuit, (ii) a plurality of second analog memory means comprising capacitors for storing said one line of separated color signals transmitted by said second switching means as analog values, and (iii) a plurality of second buffer amplifiers for amplifying said separated color signals stored in said second analog memory means, and (c) an analog pulse width modulating circuit having, (i) a plurality of analog comparators comprising differential amplifiers each for comparing one of said analog values stored in said second analog memory means after being amplified by said second buffer amplifiers with the reference analog data voltage from said control circuit, and (ii) a plurality of power switching circuits for generating column electrode driving signals each having a pulse width determined by an output of one of said analog comparators.