Patent US5153461A successfully refreshed from Google Patents.
US5153461A
Expired / Lapsed
US
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Logic circuit using element having negative differential conductance
Assignee: New Energy and Industrial Technology Development Organization
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Filing: 1990-11-30
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Granted: 1992-10-06
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Expires: 2010-11-30
Abstract
Abstract A logic circuit includes n input terminals where n is an odd integer, an output terminal, and n input resistance elements respectively connected to the n input terminals. The logic circuit also includes a negative differential conductance element having a negative differential conductance in which the negative differential conductance element outputs a peak voltage and a valley voltage higher than the peak voltage. The negative differential conductance element has a first terminal coupled to the n input terminals via the n input resistance elements, and a second terminal. The negative differential conductance element outputs a first group of voltages lower than the peak voltage to the second terminal when the number of input terminals which are at a low level is greater than the number of input terminals which are at a high level, and outputs a second group of voltages to the second terminal when the number of input terminals which are at the high level is greater than the number of input terminals which are at the low level. Further, the logic circuit includes an output circuit which outputs a first voltage indicating the first group of voltages to the output terminal and which outputs a second voltage indicating the second group of voltages.
Inventors
- 👤 Motomu Takatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:38
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/36; H03K19/00; H03K19/20; H03K19/23
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
317 words
A logic circuit comprising: n input terminals where n is an odd integer; an output terminal; n input resistance elements respectively connected to said n input terminals; a negative differential conductance element having a negative differential conductance in which said negative differential conductance element outputs a peak voltage and a valley voltage lower than said peak voltage, said negative differential conductance element having a first terminal coupled to said n input terminals via said n input resistance elements, and a second terminal, said negative differential conductance outputting a first group of voltages lower than said peak voltage to said second terminal when the ny umber of input terminals which are at a low level is greater than the number of input terminals which are at a high level, and outputting a second group of voltages to said second terminal when the number of input terminals which are at the high level is greater than the number of input terminals which are at the low level, said negative differential conductance element comprising: a transistor having a negative differential conductance and having a base coupled to said n input terminals via said n input resistance elements and serving as said first terminal, a collector connected to said base and serving as said second terminal, and an emitter set to a reference voltage; and output circuit means, coupled to the second terminal of said negative differential conductance element, for outputting a first voltage indicating said first group of voltages to said output terminal and or outputting a second voltage indicating said second group of voltages, said output circuit means comprising: a load resistance element; and a transistor having a base operatively connected to said second terminal of said negative differential conductance element, and a collector connected to said output terminal and to a first power source via said load resistance element, and an emitter connected to a second power source.
Claim 2
Dependent Claim
317 words
A logic circuit comprising: n input terminals where n is an odd integer; an output terminal; n input resistance elements respectively connected to said n input terminals; a negative differential conductance element having a negative differential conductance in which said negative differential conductance element outputs a peak voltage and a valley voltage lower than said peak voltage, said negative differential conductance element having a first terminal coupled to said n input terminals via said n input resistance elements, and a second terminal, said negative differential conductance outputting a first group of voltages lower than said peak voltage to said second terminal when the ny umber of input terminals which are at a low level is greater than the number of input terminals which are at a high level, and outputting a second group of voltages to said second terminal when the number of input terminals which are at the high level is greater than the number of input terminals which are at the low level, said negative differential conductance element comprising: a transistor having a negative differential conductance and having a base coupled to said n input terminals via said n input resistance elements and serving as said first terminal, a collector connected to said base and serving as said second terminal, and an emitter set to a reference voltage; and output circuit means, coupled to the second terminal of said negative differential conductance element, for outputting a first voltage indicating said first group of voltages to said output terminal and or outputting a second voltage indicating said second group of voltages, said output circuit means comprising: a load resistance element; and a transistor having a base operatively connected to said second terminal of said negative differential conductance element, and a collector connected to said output terminal and to a first power source via said load resistance element, and an emitter connected to a second power source.
Claim 3
Dependent Claim
80 words
A logic circuit as claimed in claim 1, wherein said negative differential conductance transistor has a first group of base-emitter voltages which corresponds to said first group of voltages and which are lower than said peak voltage at which a peak emitter current passes through said transistor, and s second group of base-emitter voltages which corresponds to said second group of voltages and which are higher than said valley voltage at which a valley emitter current passes through said transistor.
Claim 4
Dependent Claim
32 words
A logic circuit as claimed in claim 1, wherein said output circuit means further comprises: voltage divider means for dividing a voltage of said second terminal and for outputting a divided voltage.
Claim 5
Dependent Claim
58 words
A logic circuit as claimed in claim 3, wherein: said voltage divider means comprises first and second divider resistance elements connected in series between said second terminal and said second power source; and a node at which said first and second divider resistance elements are connected in series is connected to the base of said output circuit transistor.
Claim 6
Dependent Claim
141 words
A logic circuit as claimed in claim 1, wherein said negative differential conductance element comprises a first transistor having a negative differential conductance and having a base coupled to said n input terminal via said n input resistance elements and serving as said first terminal, a collector connected to said base and serving as said second terminal, and an emitter, and wherein said output circuit mans comprises: voltage divider means or dividing a voltage of said second terminal and or outputting a divided voltage; a load resistance element; and a second transistor having a base to which said divided voltage is applied, and a collector connected to said output terminal and to a first power source via said load resistance element, and an emitter connected to a second power source to which the emitter of said first transistor is also connected.
Claim 7
Dependent Claim
57 words
A logic circuit as claimed din claim 5, wherein: said voltage divider means comprises first and second divider resistance elements connected in series between said second terminal and said second power source; and a node at which said first and second divider resistance element are connected in series is connected to the base of said second transistor.
Claim 8
Dependent Claim
112 words
A logic circuit as claimed in claim 6, wherein resistance values of said n input resistance elements and said first and second divider resistance elements are selected so that said negative differential conductance element outputs the first group of voltages lower than said peak voltage to said second terminal when the number of input terminals which are at the low level is greater than the number of input terminals which are at the high level, and outputs the second group of voltages to said second terminal when the number of input terminals which are at the high level is greater than the number of input terminals which are at the low level.
Claim 9
Dependent Claim
43 words
A logic circuit as claimed in claim 1, wherein said output circuit means further comprises an emitter follower transistor having a base connected to said output terminal, the collector connected to a predetermined power source, and an emitter coupled to another output terminal.
Claim 10
Dependent Claim
26 words
A logic circuit as claimed in claim 1, further comprising inverter means, coupled to said output terminal, for inverting said first voltage and said second voltage.
Claim 11
Dependent Claim
20 words
A logic circuit as claimed in claim 1, wherein said negative differential conductance element comprises a resonant-tunneling hot electron transistor.
Claim 12
Dependent Claim
19 words
A logic circuit as claimed in claim 1, wherein said negative differential conductance element comprises a resonant-tunneling bipolar transistor.
Claim 13
Dependent Claim
18 words
A logic circuit as claimed in claim 1, wherein said negative differential conductance element comprises a resonant-tunneling diode.
Claim 14
Dependent Claim
77 words
A logic circuit as claimed in claim 1, wherein said output circuit comprises: a Zener diode having a cathode terminal connected to said second terminal, and an anode terminal; and a resistor having a first end connected to the anode terminal of said Zener diode, and a second terminal tow which a reference voltage is applied, and wherein said anode terminal of said Zener diode is connected to the first end of said resistor at a node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |