Patent US5151903A successfully refreshed from Google Patents.
US5151903A
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High efficiency pattern sequence controller for automatic test equipment
Assignee: Texas Instruments Inc
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Filing: 1989-09-28
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Granted: 1992-09-29
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Expires: 2009-09-28
Abstract
Abstract A pattern sequence control system utilizing a control RAM to provide pattern control information only when a change in pattern sequence control is required, thereby significantly reducing the amount of pattern control memory required. The pattern sequence control system utilizes a single pattern address counter for sequential patterns and a single loop address counter for looping pattern. The pattern address counter and loop address counter provide the pattern memory address for all pattern memory regardless of the number of tester channels. A cycle counter determines the number of test cycles that a sequential pattern or repeating pattern will be applied. A loop length counter and loop counter are used to control pattern looping.
Inventors
- 👤 Marc R. Mydill
- 👤 Sheila O'Keefe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
175 words
A pattern sequence control system for controlling the sequence of pattern memory addresses applied to pattern money during the execution of test cycles of functional tests for semiconductor devices, comprising; a memory for storing control information describing only changes in the sequence of a pattern that is to be executed; control logic circuits for incrementing the addresses of control information for pattern sequence changes; a single pattern address counter for incrementing the pattern addresses in memory for sequential patterns; a single loop address counter for incrementing the pattern address in memory for looping patterns; and a cycle and loop count memory storing a cycle count which represents the number of times a single pattern is to be repeated and a loop count which represents the number of times a loop is to be executed; wherein the cycle count also represents the number of sequential pattern addresses to be executed in a straight line mode, and the loop count represents the maximum number of times a match loop is to be executed before logging a failure.
Claim 2
Dependent Claim
175 words
A pattern sequence control system for controlling the sequence of pattern memory addresses applied to pattern money during the execution of test cycles of functional tests for semiconductor devices, comprising; a memory for storing control information describing only changes in the sequence of a pattern that is to be executed; control logic circuits for incrementing the addresses of control information for pattern sequence changes; a single pattern address counter for incrementing the pattern addresses in memory for sequential patterns; a single loop address counter for incrementing the pattern address in memory for looping patterns; and a cycle and loop count memory storing a cycle count which represents the number of times a single pattern is to be repeated and a loop count which represents the number of times a loop is to be executed; wherein the cycle count also represents the number of sequential pattern addresses to be executed in a straight line mode, and the loop count represents the maximum number of times a match loop is to be executed before logging a failure.
Claim 3
Dependent Claim
43 words
The pattern sequence control system according to claim 1, including a loop length counter, used in conjunction with pattern loops, that is incremented whenever the pattern address changes during the loop, and is initialized at the start of each iteration through the loop.
Claim 4
Dependent Claim
31 words
The pattern sequence control system according to claim 1, including a control RAM which provides output to alert the control system of the need for test cycles that require back-to-back changes.
Claim 5
Dependent Claim
154 words
A pattern sequence control system for controlling the sequence of pattern memory addresses applied to pattern memory during the execution of a functional test, comprising; a control RAM for storing the changes in the sequence of patterns that are to be executed; a single pattern address counter for incrementing the pattern addresses in memory for sequential patterns; and a single loop address counter for incrementing the pattern address in memory for looping patterns; and a cycle and loop count memory storing a cycle count which represents the number of times a single pattern is to be repeated and a loop count which represents the number of times a loop is to be executed; wherein the cycle count also represents the number of sequential pattern addresses to be executed in a straight line mode, and the loop count represents the maximum number of times a match loop is to be executed before logging a failure.
Claim 6
Dependent Claim
154 words
A pattern sequence control system for controlling the sequence of pattern memory addresses applied to pattern memory during the execution of a functional test, comprising; a control RAM for storing the changes in the sequence of patterns that are to be executed; a single pattern address counter for incrementing the pattern addresses in memory for sequential patterns; and a single loop address counter for incrementing the pattern address in memory for looping patterns; and a cycle and loop count memory storing a cycle count which represents the number of times a single pattern is to be repeated and a loop count which represents the number of times a loop is to be executed; wherein the cycle count also represents the number of sequential pattern addresses to be executed in a straight line mode, and the loop count represents the maximum number of times a match loop is to be executed before logging a failure.
Claim 7
Dependent Claim
57 words
The pattern sequence control system according to claim 4, wherein basic pattern control includes straight line sequential patterns, repeating patterns, and pattern loops, including; at least one counter to determine the number of test cycles a sequential sequence or repeating pattern is to be applied, and at least one address register to store a pattern starting address.
Claim 8
Dependent Claim
30 words
The pattern sequence control system according to claim 4, including a loop counter which is incremented at the beginning of each loop as it is processed through the control system.
Claim 9
Dependent Claim
43 words
The pattern sequence control system according to claim 4, including a loop length counter, used in conjunction with pattern loops, that is incremented whenever the pattern address changes during the loop, and is initialized at the start of each iteration through the loop.
Claim 10
Dependent Claim
29 words
The pattern sequence control system according to claim 4, including a cycle counter which determines the number of test cycles a sequential sequence or repeating pattern will be applied.
Claim 11
Independent Claim
134 words
A method of compression of pattern control storage and sequential patterns are to be performed during successive test cycles, comprising the steps of: storing control information in a memory describing only the changes in the sequence of a pattern that is to be executed; and incrementing the memory address for pattern sequence changes; loading a starting pattern address into a pattern address counter; loading the output of the cycle count and loop count memory into a cycle counter; and incrementing the pattern address counter until the cycle counter has reached a terminal count; wherein the cycle count also represents the number of sequential pattern addresses to be executed in a straight line mode, and the loop count represents the maximum number of times a match loop is to be executed before logging a failure.
Claim 12
Independent Claim
134 words
A method of compression of pattern control storage and sequential patterns are to be performed during successive test cycles, comprising the steps of: storing control information in a memory describing only the changes in the sequence of a pattern that is to be executed; and incrementing the memory address for pattern sequence changes; loading a starting pattern address into a pattern address counter; loading the output of the cycle count and loop count memory into a cycle counter; and incrementing the pattern address counter until the cycle counter has reached a terminal count; wherein the cycle count also represents the number of sequential pattern addresses to be executed in a straight line mode, and the loop count represents the maximum number of times a match loop is to be executed before logging a failure.
Claim 13
Dependent Claim
103 words
The method according to claim 9, wherein pattern loops are to be performed on a sequence of patterns during successive test cycles, the pattern sequence addresses are generated by a loop address counter, including the steps of: loading the output of the cycle and loop count memory into a loop counter; loading the output of a loop length memory into a loop length counter; loading the output of a loop starting address memory into a loop address counter; freezing the pattern address counter; and selecting the output of the loop address counter via a pattern address multiplexer to start a pattern address pipeline.
Claim 14
Dependent Claim
19 words
The method according to claim 9, wherein information is stored for straight line patterns, repeating patterns and pattern loops.
Claim 15
Dependent Claim
24 words
The method according to claim 9, including loading a cycle count to determine the number of test cycles a repeating pattern will be applied.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-29 | 1996-03-30 | 1996-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-29 | 2000-03-30 | 2000-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-29 | 2004-03-30 | 2004-09-29 | $7700.00 | Window Closed / Lapsed |