US5151868A
Expired / Lapsed
US
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Signal line terminal allocation method
Assignee: Hitachi Ltd
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Filing: 1990-01-31
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Granted: 1992-09-29
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Expires: 2010-01-31
Abstract
Abstract A signal line terminal allocation method includes an electronic device which is hierarchically designed to obtain terminal allocations which satisfy electrical restrictive conditions. The electronic device includes high hierarchial components and low hierarchial components; the high hierarchial components are connected to the low hierarchical components by a plurality of signal lines through a plurality of signal line terminals. The method including the steps of: 1) obtaining all the different combinations of an allocation of the signal lines to the signal line terminals; 2) calculating a plurality of signal line lengths for all the different combinations, each of the plurality of signal line lengths corresponding to a sum of the line lengths of each of the signal lines in the allocation; and 3) selecting the combinations of allocation of signal lines in which electrical restrictions corresponding to each of the plurality of signal lines are satisfied, the electrical restrictions including the maximum line length. The above method includes groups of plural signal lines of both high and low hierarchial components.
Inventors
- 👤 Yoshinori Nishiyama
- 👤 Tomoatsu Yanagita
- 👤 Masahiko Nagai
- 👤 Mitsuru Morikuni
- 👤 Kenji Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:50
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
201 words
A signal line terminal allocation method executed by a computer for an electronic device which is hierarchically designed, said electronic device comprising high hierarchial components and low hierarchial components, the high hierarchial components being connected to the low hierarchial components by a plurality of signal lines through a plurality of signal line terminals, the method comprising the steps of: obtaining all of the different plural combinations of an allocation of the plurality of signal lines to the plurality of signal line terminals; calculating a plurality of the signal line lengths for all of the different plural combinations, each of the plurality of the signal line lengths corresponding to a sum of line lengths of each of the plurality of signal lines in the allocation; selecting plural combinations of the allocation of the plurality of signal lines in which electrical restrictions corresponding to said each of the plurality of signal liens are satisfied, the electrical restrictions comprising an allowable maximum line length of said each of the plurality of signal lines; and allocating said each of the plurality of signal lines to the plurality of signal line terminals in accordance with one combination from the plural combinations which satisfies said electrical restrictions.
Claim 2
Dependent Claim
201 words
A signal line terminal allocation method executed by a computer for an electronic device which is hierarchically designed, said electronic device comprising high hierarchial components and low hierarchial components, the high hierarchial components being connected to the low hierarchial components by a plurality of signal lines through a plurality of signal line terminals, the method comprising the steps of: obtaining all of the different plural combinations of an allocation of the plurality of signal lines to the plurality of signal line terminals; calculating a plurality of the signal line lengths for all of the different plural combinations, each of the plurality of the signal line lengths corresponding to a sum of line lengths of each of the plurality of signal lines in the allocation; selecting plural combinations of the allocation of the plurality of signal lines in which electrical restrictions corresponding to said each of the plurality of signal liens are satisfied, the electrical restrictions comprising an allowable maximum line length of said each of the plurality of signal lines; and allocating said each of the plurality of signal lines to the plurality of signal line terminals in accordance with one combination from the plural combinations which satisfies said electrical restrictions.
Claim 3
Dependent Claim
28 words
The method as in claim 1, wherein said allowable maximum line length is defined by a characteristic impedance of a wiring route of the plurality of signal lines.
Claim 4
Dependent Claim
24 words
The method as in claim 1, wherein the step of selecting further includes the step of only selecting the combination having the shortest length.
Claim 5
Dependent Claim
271 words
A signal line terminal allocation method executed by a computer for an electronic device which is hierarchically designed, said electronic device comprising high hierarchial components and low hierarchial components, both the high hierarchial components and the low hierarchial components comprising plural signal lines, the plural signal lines connecting the high hierarchial components with the low hierarchical components through plural signal line terminals, the method comprising the steps of: forming plural groups of signal lines from the plural signal liens, each of the plural groups of signal lines corresponding to a signal line terminal of the plural signal line terminals; obtaining all of the different plural combinations of an allocation of the plural groups of signal lines to the plural signal line terminals; calculating a plurality of group line lengths for all of the different plural combinations, each of the plurality of the group line lengths corresponding to a sum of line lengths of each of the plural groups of signal liens in the allocation, a line length of each of the plural groups corresponding to a sum of line lengths of each of the plural signal lines of each of the plural groups; and selecting combinations of the allocation of the plural groups of the plural signal lines in which electrical restrictions corresponding to each of the plural groups of the plural signal lines are satisfied, the electrical restrictions comprising an allowable maximum line length of each of the plural signal lines; and allocating each of plural groups of plural signal lines to the plural signal line terminals in accordance with one combination from said combinations which satisfies said electrical restrictions.
Claim 6
Dependent Claim
271 words
A signal line terminal allocation method executed by a computer for an electronic device which is hierarchically designed, said electronic device comprising high hierarchial components and low hierarchial components, both the high hierarchial components and the low hierarchial components comprising plural signal lines, the plural signal lines connecting the high hierarchial components with the low hierarchical components through plural signal line terminals, the method comprising the steps of: forming plural groups of signal lines from the plural signal liens, each of the plural groups of signal lines corresponding to a signal line terminal of the plural signal line terminals; obtaining all of the different plural combinations of an allocation of the plural groups of signal lines to the plural signal line terminals; calculating a plurality of group line lengths for all of the different plural combinations, each of the plurality of the group line lengths corresponding to a sum of line lengths of each of the plural groups of signal liens in the allocation, a line length of each of the plural groups corresponding to a sum of line lengths of each of the plural signal lines of each of the plural groups; and selecting combinations of the allocation of the plural groups of the plural signal lines in which electrical restrictions corresponding to each of the plural groups of the plural signal lines are satisfied, the electrical restrictions comprising an allowable maximum line length of each of the plural signal lines; and allocating each of plural groups of plural signal lines to the plural signal line terminals in accordance with one combination from said combinations which satisfies said electrical restrictions.
Claim 7
Dependent Claim
27 words
The method as in claim 4, wherein the step of selecting further includes the step of only selecting the combination of said combinations having the shortest length.
Claim 8
Dependent Claim
23 words
The method as in claim 4, wherein the electrical restrictions correspond to conditions of the plural signal lines of each of the groups.
Claim 9
Dependent Claim
18 words
The method as in claim 4, wherein said allowable maximum line length is defined as signal delay times.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-29 | 1996-03-30 | 1996-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-29 | 2000-03-30 | 2000-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-29 | 2004-03-30 | 2004-09-29 | $7700.00 | Window Closed / Lapsed |