Data converting apparatus

Claim 2

A data converting apparatus for converting an input data series being expressed in binary codes into an output data series, which comprises: insertion means for repetitively inserting one of a predetermined number of DC control bits into an input data series, at every predetermined bit interval to thereby generate a redundant data series; encoding means for subjecting said redundant data series to a code conversion operation under a preselected conversion rule so as to generate said output data series; and selection means for selecting a binary code for said one of predetermined number of DC control bits as a function of a DC component of said output data series.

Claim 3

A data converting apparatus according to claim 1, and further comprising means for acquiring the output data series for each of two or more data values prepared in advance as the DC control bits, and determining any one of the data values as redundant data by referring to a result of DC control of the output data series.

Claim 4

Apparatus for converting an input data series, comprising: a first data conversion channel comprising a first redundant data series generator means having an input coupled to an input data series and an output coupled to an input of a first code converter means, said first code converter means having an output coupled to a first input of a selector means, said first redundant data series generator means inserting a first code into said input data series at predetermined intervals; a second data conversion channel comprising a second redundant data series generator means having an input coupled to the input data series and an output coupled to an input of a second code converter means, said second code converter means having an output coupled to a second input of said selector means, said second redundant data series generator means inserting a second code into said input data series at the predetermined intervals, said selector means having an output for expressing an output data series, the output data series being either said input from said first code converter means or said input from said second code converter means; first digital sum value calculating means having an input coupled to said output of said first code converter means; second digital sum value calculating means having an input coupled to said output of said second code converter means; third digital sum value calculating means having an input coupled to said output of said selector means for receiving said output data series therefrom; and control means having inputs coupled to an output of said first digital sum value calculating means, an output of said second digital sum value calculating means, and an output of said third digital sum value calculating means, said control means having an output coupled to said selecting means and, responsive to said outputs of said first, second, and third digital sum value calculating means, controlling said output to select either the first input or the second input to said selector means to appear as said output data series so as to minimize an absolute value of the digital sum value of the output data series.

Claim 5

Apparatus for converting an input data series, comprising: a first data conversion channel comprising a first redundant data series generator means having an input coupled to an input data series and an output coupled to an input of a first code converter means, said first code converter means having an output coupled to a first input of a selector means, said first redundant data series generator means inserting a first code into said input data series at predetermined intervals; a second data conversion channel comprising a second redundant data series generator means having an input coupled to the input data series and an output coupled to an input of a second code converter means, said second code converter means having an output coupled to a second input of said selector means, said second redundant data series generator means inserting a second code into said input data series at the predetermined intervals, said selector means having an output for expressing an output data series, the output data series being either said input from said first code converter means or said input from said second code converter means; first digital sum value calculating means having an input coupled to said output of said first code converter means; second digital sum value calculating means having an input coupled to said output of said second code converter means; third digital sum value calculating means having an input coupled to said output of said selector means for receiving said output data series therefrom; and control means having inputs coupled to an output of said first digital sum value calculating means, an output of said second digital sum value calculating means, and an output of said third digital sum value calculating means, said control means having an output coupled to said selecting means and, responsive to said outputs of said first, second, and third digital sum value calculating means, controlling said output to select either the first input or the second input to said selector means to appear as said output data series so as to minimize an absolute value of the digital sum value of the output data series.

Claim 6

Apparatus as set forth in claim 3 and further comprising means, coupled to the input of said first and said second redundant data series generator means, for randomizing said input data series so as to diffuse frequency components thereof.

Claim 7

Apparatus as set forth in claim 3 and further comprising: first means, interposed between said output of said first code converter means and said first input of said selector means, for inserting a synchronizing signal into said output of said first code converter means; and second means, interposed between said output of said second code converter means and said second input of said selector means, for inserting a synchronizing signal into said output of said second code converter means.

Claim 8

Apparatus as set forth in claim 3 and further comprising: first means, interposed between said output of said first code converter means and said first input of said selector means, for delaying said output of said first code converter means by a predetermined number of bits; and second means, interposed between said output of said second code converter means and said second input of said selector means, for delaying said output of said second code converter means by the predetermined number of bits.

Claim 9

Apparatus as set forth in claim 6 wherein the predetermined number of bits equals 192.

Claim 10

Apparatus as set forth in claim 3 wherein said first code is comprised of two binary zeros and wherein said second code is comprised of two binary ones.

Claim 11

Apparatus as set forth in claim 8 wherein said first code converter means converts said two binary zeros into a three bit code of "010" and wherein said second code converter means converts said two binary ones into a first three bit code of "101" or into a second three bit code of "000".

Claim 12

Apparatus as set forth in claim 3 wherein each of said predetermined intervals has a duration of 126 bits.

Claim 13

Apparatus as set forth in claim 3 and further comprising means for resetting said first and said second digital sum value calculating means prior to the beginning of each of said predetermined intervals.

Claim 14

Apparatus as set forth in claim 3 wherein said control means includes: means for adding the output of said first digital sum value calculating means to said output of said third digital sum value calculating means; means for adding the output of said second digital sum value calculating means to said output of said third digital sum value calculating means; and means, responsive to a sum obtained by said first adding means and to a sum obtained by said second adding means, for controlling said output to select either the first input or the second input to said selector means.

Claim 15

Apparatus as set forth in claim 3 and further comprising means for NRZI modulating said output data series.

Claim 18

A method as set forth in claim 14 wherein the step of inserting includes an initial step of randomizing the input data series so as to diffuse frequency components thereof.

Claim 19

A method as set forth in claim 14 wherein the step of code converting includes a further step of inserting a synchronizing signal into the code converted redundant data series.

Claim 20

A method as set forth in claim 16 wherein the step of inserting a synchronizing signal is followed by a step of delaying the code converted and synchronized redundant data series by a predetermined number of bits.

Claim 21

A method as set forth in claim 17 wherein the predetermined number of bits equals 192.

Claim 22

A method as set forth in claim 14 wherein each of said predetermined intervals has a duration of 126 bits.

Claim 23

A data converting apparatus for converting an input data series being expressed in binary codes into an output data series, which comprises: DC control code insertion means for repetitively inserting a plurality of DC control codes into said input data series at every predetermined bit interval so as to produce a plurality of redundant data series, each containing one of said DC control codes at said predetermined bit interval; encoding means for subjecting said redundant data series to a code conversion operation under a preselected conversion rule, respectively, so as to produce encoded data series; DSV detection means for detecting DSV's for said encoded data series, respectively, for every period of said predetermined bit interval; and selection means for selecting either one of said encoded data series for every period of said predetermined bit interval while comparing the detected DSV's with each other so as to produce said output data series.

Claim 24

A data converting apparatus for converting an input data series being expressed in binary codes into an output data series, which comprises: DC control code insertion means for repetitively inserting a plurality of DC control codes into said input data series at every predetermined bit interval so as to produce a plurality of redundant data series, each containing one of said DC control codes at said predetermined bit interval; encoding means for subjecting said redundant data series to a code conversion operation under a preselected conversion rule, respectively, so as to produce encoded data series; DSV detection means for detecting DSV's for said encoded data series, respectively, for every period of said predetermined bit interval; and selection means for selecting either one of said encoded data series for every period of said predetermined bit interval while comparing the detected DSV's with each other so as to produce said output data series.