Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode

Claim 1

A method of forming a thin film field effect transistor having a drain-channel P-N junction that is distanced from a gate electrode comprising: depositing a first thin polycrystalline silicon layer doped with a first type impurity for semiconductors over a first thin insulating layer on a monocrystalline silicon substrate; depositing a second thin insulating layer over the surface of said first polycrystalline silicon layer; forming a second polycrystalline silicon layer over at least said second insulating layer; depositing a third insulating layer over said second polycrystalline silicon layer; removing portions of said second polycrystalline silicon layer and overlying third insulating layer, leaving a gate area portion over a portion of the first polycrystalline silicon layer, the edges of the remaining portion of said second polycrystalline silicon layer being exposed; introducing second opposite type impurity ions into said first polycrystalline layer by ion bombardment to form source and drain regions therein, the remaining gate electrode area portion of said second polycrystalline silicon layer and said third overlying insulating layer forming a mask thereby preventing ions from penetrating the underlying area of said first polysilicon layer to form a channel region positioned between said source and drain regions and defined by the drain channel P-N junction and the source channel P-N junction; forming a masking layer that covers at least a portion of the edge of the second polycrystalline silicon layer over the source-channel P-N junction in said first polycrystalline silicon layer; etching back the exposed edge portion of said second polycrystalline silicon layer above the drain-channel P-N junction in said first polycrystalline silicon 5 layer; and removing said masking layer and forming an overlying insulating layer over the surface of the resultant device.

Claim 2

A method of forming a thin film field effect transistor having a drain-channel P-N junction that is distanced from a gate electrode comprising: depositing a first thin polycrystalline silicon layer doped with a first type impurity for semiconductors over a first thin insulating layer on a monocrystalline silicon substrate; depositing a second thin insulating layer over the surface of said first polycrystalline silicon layer; forming a second polycrystalline silicon layer over at least said second insulating layer; depositing a third insulating layer over said second polycrystalline silicon layer; removing portions of said second polycrystalline silicon layer and overlying third insulating layer, leaving a gate area portion over a portion of the first polycrystalline silicon layer, the edges of the remaining portion of said second polycrystalline silicon layer being exposed; introducing second opposite type impurity ions into said first polycrystalline layer by ion bombardment to form source and drain regions therein, the remaining gate electrode area portion of said second polycrystalline silicon layer and said third overlying insulating layer forming a mask thereby preventing ions from penetrating the underlying area of said first polysilicon layer to form a channel region positioned between said source and drain regions and defined by the drain channel P-N junction and the source channel P-N junction; forming a masking layer that covers at least a portion of the edge of the second polycrystalline silicon layer over the source-channel P-N junction in said first polycrystalline silicon layer; etching back the exposed edge portion of said second polycrystalline silicon layer above the drain-channel P-N junction in said first polycrystalline silicon 5 layer; and removing said masking layer and forming an overlying insulating layer over the surface of the resultant device.

Claim 10

A method of forming a thin film field effect transistor having a drain-channel P-N junction that is distanced from a gate electrode comprising: depositing a first thin polycrystalline silicon layer doped with a first type impurity for semiconductors over a first thin insulating layer on a monocrystalline silicon substrate; depositing a second thin insulating layer over the surface of said first polycrystalline silicon layer: forming a second polycrystalline silicon layer over at least said second insulating layer; depositing a third insulating layer over said second polycrystalline silicon layer; removing portions of said second polycrystalline silicon layer and overlying third insulating layer, leaving a gate area portion over a portion of the first polycrystalline silicon layer, the edges of the remaining portion of said silicon polycrystalline silicon layer being exposed; forming a masking layer that covers at least a portion of the edge of the second polycrystalline silicon layer, but leaves the opposite edge exposed; etching back the exposed edge portion of said second polycrystalline silicon layer; removing the masking layer; and introducing second opposite type impurity ions into said first polycrystalline silicon layer by ion bombardment to form source and drain regions therein, the overlying third insulating layer forming a mask which prevents ions from penetrating said first polycrystalline silicon layer thereby forming a channel region, positioned between said source and drain regions and defined by the drain channel P-N junction and the source channel P-N junction; wherein the second polycrystalline layer forms the gate electrode with the edge thereof spaced from the drain-channel junction.

Claim 11

A method of forming a thin film field effect transistor having a drain-channel P-N junction that is distanced from a gate electrode comprising: depositing a first thin polycrystalline silicon layer doped with a first type impurity for semiconductors over a first thin insulating layer on a monocrystalline silicon substrate; depositing a second thin insulating layer over the surface of said first polycrystalline silicon layer: forming a second polycrystalline silicon layer over at least said second insulating layer; depositing a third insulating layer over said second polycrystalline silicon layer; removing portions of said second polycrystalline silicon layer and overlying third insulating layer, leaving a gate area portion over a portion of the first polycrystalline silicon layer, the edges of the remaining portion of said silicon polycrystalline silicon layer being exposed; forming a masking layer that covers at least a portion of the edge of the second polycrystalline silicon layer, but leaves the opposite edge exposed; etching back the exposed edge portion of said second polycrystalline silicon layer; removing the masking layer; and introducing second opposite type impurity ions into said first polycrystalline silicon layer by ion bombardment to form source and drain regions therein, the overlying third insulating layer forming a mask which prevents ions from penetrating said first polycrystalline silicon layer thereby forming a channel region, positioned between said source and drain regions and defined by the drain channel P-N junction and the source channel P-N junction; wherein the second polycrystalline layer forms the gate electrode with the edge thereof spaced from the drain-channel junction.