Method and system for minimizing power demands on portable computers and the like by refreshing selected dram cells

Claim 3

The method defined in claim 1 which further includes the steps of: a. reading another computer software program to ascertain how much RAM memory is required thereby, and b. refreshing another selected fraction or subset of the total number of rows in said single RAM memory chips as required by said another computer program in addition to the fraction or subset of the total number of rows required by the first computer program and at a controlled refresh frequency corresponding to an operational power level sufficient to prevent any cell within said second number of selected rows in said RAM memory from losing data stored therein.

Claim 4

The method defined in claim 1 which further includes: a. reading said computer program and thereby determining the number of rows of said memory elements or cells in said RAM necessary for the retention of data therein when said computer is operating in a standby mode, and b. refreshing the determined number of rows at a controlled refresh frequency and power level necessary to retain data in said determined number of rows until said computer is brought out of said standby mode.

Claim 7

The system defined in claim 4 which further includes: a. means for reading another computer software program to ascertain how much RAM memory is required thereby, and b. means connected to said reading means for refreshing another selected fraction or subset of the total number of rows in a single RAM memory chip as required by said another computer program in addition to the fraction or subset of the total number of rows required by the first computer program and at a controlled refresh frequency corresponding to an operational power level sufficient to prevent any cell within said another selected number of selected rows in said RAM memory chip from losing data stored therein.

Claim 8

The system defined in claim 4 which further includes: a. means for reading a computer program and thereby determining the number of rows of said memory elements or cells in said RAM necessary for the retention of data therein when said computer is operating in a standby mode, and b. means connected to said determining means for refreshing the determined number of rows at a controlled refresh frequency and power level necessary to retain data in said determined number of rows until said computer is brought out of said standby mode.

Claim 9

A computer system operative for refreshing certain percentage of RAM memory capacity on a required use basis, and further operative for changing said percentage of RAM memory upon changing to a different software application, said system including, in combination: a. a central processing unit, b. a random access memory (RAM) stage comprising a RAM memory chip having a certain number of rows of memory elements or cells therein, and c. random access memory (RAM) control means connected between said central processing unit and said random access memory stage and responsive to input data signals received from said central processing unit for refreshing a selected fraction or subset of the total number of rows of memory elements or cells within said RAM stage, but less than the total number of rows of elements or cells in one or more RAM memory chips within said RAM storage in order to conserve power, as a function of memory storage capacity requirements for a software program used by said central processing unit.

Claim 10

A computer system operative for refreshing certain percentage of RAM memory capacity on a required use basis, and further operative for changing said percentage of RAM memory upon changing to a different software application, said system including, in combination: a. a central processing unit, b. a random access memory (RAM) stage comprising a RAM memory chip having a certain number of rows of memory elements or cells therein, and c. random access memory (RAM) control means connected between said central processing unit and said random access memory stage and responsive to input data signals received from said central processing unit for refreshing a selected fraction or subset of the total number of rows of memory elements or cells within said RAM stage, but less than the total number of rows of elements or cells in one or more RAM memory chips within said RAM storage in order to conserve power, as a function of memory storage capacity requirements for a software program used by said central processing unit.

Claim 11

The system defined in claim 7 which further includes means for receiving a portable read-only-memory (ROM) card which is connected to said random access memory stage so that data from said read-only-memory card may be loaded into said random access memory stage during start-up of said computer system.

Claim 12

The system defined in claim 7 wherein said random access memory control means includes: a. an interface input logic stage connected to receive input data from said central processing unit, b. a start address register and a row number selection register connected to the output of said interface input logic stage for storing the number of rows of memory elements or cells within said RAM stage to be refreshed, c. a timer stage connected to the output of said interface input logic stage for controlling the refresh frequency for said RAM stage, and d. an address increment counter and a row counter each connected to the outputs of said start address register and said row number selection register, respectively, for generating output data for refreshing said RAM state, whereby said registers, timer, and counters defined in paragraphs b., c., and d. herein may be fabricated on the same semiconductor chip that contains random access memory within said RAM state.

Claim 13

The system defined in claim 9 which further includes: a. an output address buffer and signal multiplexing stage connected to the output of said address increment counter for providing an output data stream for application to said RAM stage, and b. a RAM control output logic stage connected to receive low power mode signals and output data from said input logic interface stage for generating row access strobe (RAS) signals and column access strobe signals (CAS) for application to said RAM stage, whereby said RAM semiconductor chip may be either read, written into, or refreshed.

Claim 14

The computer system defined in claim 10 which further includes means for receiving portable read-only-memory (ROM) cards each having stored therein a known software program and connected to both said central processing unit and to said random access memory stage for loading data into said RAM stage.