Patent US5148387A successfully refreshed from Google Patents.
US5148387A
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Logic circuit and data processing apparatus using the same
Assignee: Hitachi Ltd
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Filing: 1990-02-15
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Granted: 1992-09-15
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Expires: 2010-02-15
Abstract
Abstract A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.
Inventors
- 👤 Kazuo Yano
- 👤 Koichiro Ishibashi
- 👤 Tetsuya Nakagawa
- 👤 Katsuhiro Shimohigashi
- 👤 Osamu Minato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/5016
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
389 words
A logic circuit, comprising: (1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and (2) first to fifth nodes; wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node, wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node, wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node, wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node, wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node, wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node, wherein a first input signal is supplied to said first node, wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element, wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element, wherein a third input signal is supplied to said second node, wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element, wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element; and wherein a signal related to said first, second and third input signals is generated from said fifth node.
Claim 2
Dependent Claim
389 words
A logic circuit, comprising: (1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and (2) first to fifth nodes; wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node, wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node, wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node, wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node, wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node, wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node, wherein a first input signal is supplied to said first node, wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element, wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element, wherein a third input signal is supplied to said second node, wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element, wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element; and wherein a signal related to said first, second and third input signals is generated from said fifth node.
Claim 3
Dependent Claim
21 words
A logic circuit according to claim 1, wherein said first to sixth switching elements are constituted by field effect transistors, respectively.
Claim 4
Dependent Claim
29 words
A data processing apparatus including a full adder, wherein said full adder includes a carry signal generating circuitry constituted by the logic circuit as set forth in claim 1.
Claim 5
Dependent Claim
22 words
A data processing apparatus according to claim 3, wherein said first to sixth switching elements are constituted by field effect transistors, respectively.
Claim 6
Dependent Claim
407 words
A logic circuit, comprising: (1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and (2) first to fifth nodes; wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node. wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node. wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node, wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node, wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node, wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node. wherein a first input signal is supplied to said first node, wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element, wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element, wherein a third input signal is supplied to said second node, wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element, wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element, wherein a signal related to said first, second and third input signals is generated from said fifth node, and wherein said generated signal is a carry output signal related to said first, second and third input signals.
Claim 7
Dependent Claim
407 words
A logic circuit, comprising: (1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and (2) first to fifth nodes; wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node. wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node. wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node, wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node, wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node, wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node. wherein a first input signal is supplied to said first node, wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element, wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element, wherein a third input signal is supplied to said second node, wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element, wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element, wherein a signal related to said first, second and third input signals is generated from said fifth node, and wherein said generated signal is a carry output signal related to said first, second and third input signals.
Claim 8
Dependent Claim
21 words
A logic circuit according to claim 5, wherein said first to sixth switching elements are constituted by field effect transistors, respectively.
Claim 9
Dependent Claim
408 words
A logic circuit, comprising: (1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and (2) first to fifth nodes; wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node, wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node, wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node, wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node, wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node, wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node, wherein a first input signal is supplied to said first node, wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element, wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element, wherein a third input signal is supplied to said second node, wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element, wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element, wherein a signal related to said first, second and third input signals is generated from said fifth node, and wherein said generated signal is a majority decision output signal related to said first, second and third input signals.
Claim 10
Dependent Claim
408 words
A logic circuit, comprising: (1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and (2) first to fifth nodes; wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node, wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node, wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node, wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node, wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node, wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node, wherein a first input signal is supplied to said first node, wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element, wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element, wherein a third input signal is supplied to said second node, wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element, wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element, wherein a signal related to said first, second and third input signals is generated from said fifth node, and wherein said generated signal is a majority decision output signal related to said first, second and third input signals.
Claim 11
Dependent Claim
21 words
A logic circuit according to claim 7, wherein said first to sixth switching elements are constituted by field effect transistors, respectively.
References Cited (Backward Citations)
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