Adder-subtracter for signed absolute values

Claim 2

An adder-subtracter for signed absolute values in which addition or subtraction of signed absolute values is executed in two's complement representation form and an executed result is output as a signed absolute value, the adder-subtracter comprising: a first arithmetic circuit for executing an ordinary subtractive operation in said two's complement representation form in which 1 is added to an addition result between an ivnerted subtrahend and a minuend in subtraction; a second arithmetic circuit for executing addition between an inverted subtrahend and a minuend in subtraction without adding 1 to an executed result; a sign-generating circuit, coupled to said first and second arithmetic circuits, for determining a sign of a subtraction result in said first arithmetic circuit and said second arithmetic circuit; an output-selecting circuit for selecting either one of two outputs from said first and second arithmetic circuits, according to an output from said sign-generating circuit; and an output inverter for executing bit-inversion of an output from said output-selecting circuit, according to another output from said sign-generating circuit.

Claim 3

The adder-subtracter as claimed in claim 1, wherein said first arithmetic circuit has an input bit-inverter.

Claim 4

The adder-subtracter as claimed in claim 1, wherein said first arithmetic circuit has an extended digit in a higher position of input digits, and an output from said extended digit is introduced into said sign-generating circuit to determine a sign of an operation.

Claim 5

The adder-subtracter as claimed in claim 1, wherein said sign-generating circuit determines said sign of said operation by introducing an output from a highest digit of said first arithmetic circuit.

Claim 6

The adder-subtracter as claimed in claim 1, wherein said first arithmetic circuit, second arithmetic circuit, output-selecting circuit, and output inverter are provided respectively for each of bit blocks comprised of a plurality of bits divided from input signals.

Claim 7

The adder-subtracter as claimed in claim 1, further comprising an arithmetic operation circuit including said first and second arithmetic circuits.

Claim 8

An adder-subtracter for signed absolute values, in which addition or subtraction of signed absolute values is executed in two's complement representation form and an executed result is output as a signed absolute value, the adder-subtracter comprising: an input bit-inverter from which an addend is output without inversion in addition and a subtrahend is output with inversion in subtraction; a first arithmetic circuit for executing an ordinary subtractive operation in said two's complement representation in which 1 is added to a result of adding between an output from said input bit-inverter and an augend or a minuend in subtraction; a second arithmetic circuit for executing addition between another output from said input-bit inverter and an augend or a minuend in subtraction without adding 1 to an executed result; a sign-generating circuit, coupled to said first and second arithmetic circuits, for determining whether an operation is addition or subtraction and for determining a sign of an operational result from said first arithmetic circuit; an output-selecting circuit, coupled to said sign-generating circuit and to said first and second arithmetic circuits, for selecting an output from said second arithmetic circuit to be output when an operation is determined to be addition or when an oepration is subtraction and said operational result in said first arithmetic circuit is negative as determined by said sign-generating circuit, and for selecting an output from said first arithmetic circuit to be output in other situations; and an output bit-inverter, for bit-inverting an output from said output-selecting circuit to be output when an operation is determined to be a subtraction and said output from said first arithmetic circuit is negative as determined by said sign-generating circuit, and for not bit-inverting an output from said output-selecting circuit in other situations.

Claim 9

An adder-subtracter for signed absolute values, in which addition or subtraction of signed absolute values is executed in two's complement representation form and an executed result is output as a signed absolute value, the adder-subtracter comprising: an input bit-inverter from which an addend is output without inversion in addition and a subtrahend is output with inversion in subtraction; a first arithmetic circuit for executing an ordinary subtractive operation in said two's complement representation in which 1 is added to a result of adding between an output from said input bit-inverter and an augend or a minuend in subtraction; a second arithmetic circuit for executing addition between another output from said input-bit inverter and an augend or a minuend in subtraction without adding 1 to an executed result; a sign-generating circuit, coupled to said first and second arithmetic circuits, for determining whether an operation is addition or subtraction and for determining a sign of an operational result from said first arithmetic circuit; an output-selecting circuit, coupled to said sign-generating circuit and to said first and second arithmetic circuits, for selecting an output from said second arithmetic circuit to be output when an operation is determined to be addition or when an oepration is subtraction and said operational result in said first arithmetic circuit is negative as determined by said sign-generating circuit, and for selecting an output from said first arithmetic circuit to be output in other situations; and an output bit-inverter, for bit-inverting an output from said output-selecting circuit to be output when an operation is determined to be a subtraction and said output from said first arithmetic circuit is negative as determined by said sign-generating circuit, and for not bit-inverting an output from said output-selecting circuit in other situations.

Claim 10

The adder-subtracter as claimed in claim 7, wherein said input bit-inverter, first arithmetic circuit, second arithmetic circuit, output-selecting circuit, and output bit-inverter are provided respectively for each of bit blocks comprised of a plurality of bits divided from input signals.

Claim 11

The adder-subtracter as claimed in claim 7, further comprising an arithmetic operation circuit including said first and second arithmetic circuits.

Claim 12

An adder-subtracter for signed absolute values in which addition or subtraction of signed absolute values is executed in two's complement representation form and an executed result is output as sign-magnitude representation, the adder-subtracter comprising: an input bit-inverter from which an addend is output without inversion in addition and a subtrahend is output with inversion in subtraction; a signal-generating circuit for generating a carry-propagation signal and carry generation signal of each digit according to an output from said bit-inverter and an augend or a minuend; a first carry-calculating circuit in which a carry operation to each bit of input from said signal-generating circuit is executed with a carry from a lower digit; a second carry-calculating circuit in which a carry operation to each bit of input from said signal-generating circuit is executed without a carry from a lower digit; a sign-generating circuit responsive to carrys from highest digits of said first and second carry-calculating circuits for determining signs of subtraction results; an output-selecting circuit for selecting either one of outputs form said first and second carry-calculating circuits according to an output from said sign generating-circuit; and an output circuit, to which either one of said outputs from said first and second carry-calculating circuits selected by said output-selecting circuit and a carry generated by said signal-generating circuit are input, for producing a final adding result, and for bit-inverting an input carry or adding result when a sign of subtraction is determined to be negative.

Claim 13

An adder-subtracter for signed absolute values in which addition or subtraction of signed absolute values is executed in two's complement representation form and an executed result is output as sign-magnitude representation, the adder-subtracter comprising: an input bit-inverter from which an addend is output without inversion in addition and a subtrahend is output with inversion in subtraction; a signal-generating circuit for generating a carry-propagation signal and carry generation signal of each digit according to an output from said bit-inverter and an augend or a minuend; a first carry-calculating circuit in which a carry operation to each bit of input from said signal-generating circuit is executed with a carry from a lower digit; a second carry-calculating circuit in which a carry operation to each bit of input from said signal-generating circuit is executed without a carry from a lower digit; a sign-generating circuit responsive to carrys from highest digits of said first and second carry-calculating circuits for determining signs of subtraction results; an output-selecting circuit for selecting either one of outputs form said first and second carry-calculating circuits according to an output from said sign generating-circuit; and an output circuit, to which either one of said outputs from said first and second carry-calculating circuits selected by said output-selecting circuit and a carry generated by said signal-generating circuit are input, for producing a final adding result, and for bit-inverting an input carry or adding result when a sign of subtraction is determined to be negative.

Claim 14

The adder-subtracter as claimed in claim 10, wherein said output circuit executes bit-inversion of said input carry first, and then produces an adding result by using an inverted sum of each bit when a subtractive result determined by said sign-generating circuit is negative.

Claim 15

The adder-subtracter as claimed in claim 10, wherein said input bit-inverter, signal-generating circuit, first carry-calculating circuit, second carry-calculating circuit, output-selecting circuit, and output circuit are provided respectively for each of bit blocks comprised of a plurality of bits divided from input signals.