Patent US5148255A successfully refreshed from Google Patents.
US5148255A
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US
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Semiconductor memory device
Assignee: Hitachi Ltd
•
Filing: 1991-01-23
•
Granted: 1992-09-15
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Expires: 2011-01-23
Abstract
Abstract Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
Inventors
- 👤 Shinji Nakazato
- 👤 Hideaki Uchida
- 👤 Yoshikazu Saito
- 👤 Masahiro Yamamura
- 👤 Yutaka Kobayashi
- 👤 Takahide Ikeda
- 👤 Ryoichi Hori
- 👤 Goro Kitsukawa
- 👤 Kiyoo Itoh
- 👤 Nobuo Tanba
- 👤 Takao Watanabe
- 👤 Katsuhiro Shimohigashi
- 👤 Noriyuki Homma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:12
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D89/00; H10D89/211; H10D89/213
Claims Analysis
Total Claims: 67
Claim 1
Independent Claim
150 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a further semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said further semiconductor region contacts said buried layer and extends up to the main surface of said semiconductor layer.
Claim 2
Dependent Claim
150 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a further semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said further semiconductor region contacts said buried layer and extends up to the main surface of said semiconductor layer.
Claim 3
Dependent Claim
44 words
A memory device according to claim 1, wherein said further semiconductor region, together with said buried layer, acts as a shield so as to prevent minority carriers in said semiconductor substrate and said semiconductor layer from entering said memory array and destroying said information.
Claim 4
Dependent Claim
20 words
A memory device according to claim 1, wherein said further semiconductor region extends so as to surround said memory array.
Claim 5
Dependent Claim
42 words
A memory device according to claim 1, wherein the memory cells include a switching MOSFET, wherein said buried layer is provided under the switching MOSFET, and wherein said buried layer acts to prevent a depletion layer from spreading beneath said switching MOSFET.
Claim 6
Dependent Claim
23 words
A memory device according to claim 4, wherein said buried layer is positioned such that said depletion layer reaches to said buried layer.
Claim 7
Dependent Claim
21 words
A memory device according to claim 1, wherein said bipolar transistor forms part of a peripheral circuit of the memory device.
Claim 8
Dependent Claim
25 words
A memory device according to claim 6, wherein said peripheral circuit further includes n-channel and p-channel MOS transistors forming complementary metal-oxide semiconductor field effect transistors.
Claim 9
Dependent Claim
21 words
A memory device according to claim 1, further comprising n-channel and p-channel MOS transistors forming complementary metal-oxide semiconductor field effect transistors.
Claim 10
Dependent Claim
189 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said bipolar transistor and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a second conductivity type, opposite to said first conductivity type; and a further semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said further semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer.
Claim 11
Dependent Claim
189 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said bipolar transistor and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a second conductivity type, opposite to said first conductivity type; and a further semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said further semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer.
Claim 12
Dependent Claim
45 words
A memory device according to claim 9, wherein said further semiconductor region, together with said first buried layer, acts as a shield so as to prevent minority carriers in said semiconductor substrate and said semiconductor layer from entering said memory array and destroying said information.
Claim 13
Dependent Claim
20 words
A memory device according to claim 9, wherein said further semiconductor region extends so as to surround said memory array.
Claim 14
Dependent Claim
42 words
A memory device according to claim 9, wherein the memory cells include a switching MOSFET, wherein said buried layer is provided under the switching MOSFET, and wherein said buried layer acts to prevent a depletion layer from spreading beneath said switching MOSFET.
Claim 15
Dependent Claim
23 words
A memory device according to claim 12, wherein said buried layer is positioned such that said depletion layer reaches to said buried layer.
Claim 16
Dependent Claim
191 words
A memory device comprising: a semiconductor substrate of P-type conductivity; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said bipolar transistor and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a N-type conductivity, opposite to said P-type conductivity; and a further semiconductor region, of said N-type conductivity and being formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said further semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer.
Claim 17
Dependent Claim
191 words
A memory device comprising: a semiconductor substrate of P-type conductivity; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said bipolar transistor and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a N-type conductivity, opposite to said P-type conductivity; and a further semiconductor region, of said N-type conductivity and being formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said further semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer.
Claim 18
Dependent Claim
47 words
A memory device according to claim 14, wherein said semiconductor layer is an epitaxial layer, of said N-type conductivity, and wherein said memory cell array is formed on a main surface of a P-type well region which is formed in said epitaxial layer of said N-type conductivity.
Claim 19
Dependent Claim
39 words
A memory device according to claim 15, wherein said P-type well region extends from a main surface of said epitaxial layer to said first buried layer and has an impurity concentration lower than that of said first buried layer.
Claim 20
Dependent Claim
61 words
A memory device according to claim 16, wherein each MOS memory cell of said memory array has at least one n-channel MOSFET having source and drain regions which are formed in said P-type well region, and wherein said first buried layer acts to prevent a depletion layer, which generates around said source and drain regions, from spreading beneath said n-channel MOSFET.
Claim 21
Dependent Claim
25 words
A memory device according to claim 17, wherein said first buried layer is positioned such that said depletion layer reaches to said first buried layer.
Claim 22
Dependent Claim
215 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said bipolar transistor and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a second conductivity type, opposite to said first conductivity type; a first semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said first semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer; and a second semiconductor region of said second conductivity type, said second semiconductor region being provided under said first buried layer and contacting said first semiconductor region.
Claim 23
Dependent Claim
215 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a bipolar transistor formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said bipolar transistor and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a second conductivity type, opposite to said first conductivity type; a first semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor, wherein said first semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer; and a second semiconductor region of said second conductivity type, said second semiconductor region being provided under said first buried layer and contacting said first semiconductor region.
Claim 24
Dependent Claim
50 words
A memory device according to claim 19, wherein said first semiconductor region and said second semiconductor region, together with said first buried layer, act as a shield so as to prevent minority carriers in said semiconductor substrate and said semiconductor layer from entering said memory array and destroying said information.
Claim 25
Dependent Claim
20 words
A memory device according to claim 19, wherein said first semiconductor region extends so as to surround said memory array.
Claim 26
Dependent Claim
28 words
A memory device according to claim 19, wherein said second semiconductor region, together with said first semiconductor region, surrounds both said memory array and said first buried layer.
Claim 27
Dependent Claim
44 words
A memory device according to claim 19, wherein said memory cells include a switching MOSFET, wherein said first buried layer is provided under the switching MOSFET, and wherein said first buried layer acts to prevent a depletion layer from spreading beneath said switching MOSFET.
Claim 28
Dependent Claim
24 words
A memory device according to claim 23, wherein said buried layer is positioned such that said depletion layer reaches to said first buried layer.
Claim 29
Dependent Claim
200 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a peripheral circuit including a bipolar transistor and a MOSFET, formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said peripheral circuit and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a second conductivity type, opposite to said first conductivity type; and a further semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor of said peripheral circuit, wherein said further semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer.
Claim 30
Dependent Claim
200 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a peripheral circuit including a bipolar transistor and a MOSFET, formed on said main surface of said semiconductor layer; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a second buried layer provided under said peripheral circuit and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of a second conductivity type, opposite to said first conductivity type; and a further semiconductor region formed in said semiconductor layer between said memory array and said bipolar transistor of said peripheral circuit, wherein said further semiconductor region contacts said first buried layer and extends up to the main surface of said semiconductor layer.
Claim 31
Dependent Claim
45 words
A memory device according to claim 25, wherein said further semiconductor region, together with said first buried layer, acts as a shield so as to prevent minority carriers in said semiconductor substrate and said semiconductor layer from entering said memory array and destroying said information.
Claim 32
Dependent Claim
20 words
A memory device according to claim 25, wherein said further semiconductor region extends so as to surround said memory array.
Claim 33
Dependent Claim
43 words
A memory device according to claim 25, wherein said memory cells include a switching MOSFET, wherein said first buried layer is provided under the switching MOSFET, and wherein said buried layer acts to prevent a depletion layer from spreading beneath said switching MOSFET.
Claim 34
Dependent Claim
23 words
A memory device according to claim 28, wherein said buried layer is positioned such that the depletion layer reaches to said buried layer.
Claim 35
Dependent Claim
46 words
A memory device according to claim 25, wherein said second buried layer extends under at least said bipolar transistor of said peripheral circuit, and wherein said bipolar transistor is formed in a well region of said second conductivity type which is formed in said semiconductor layer.
Claim 36
Dependent Claim
29 words
A memory device according to claim 30, wherein a collector region of said bipolar transistor comprises said well region of said second conductivity type and said second buried layer.
Claim 37
Dependent Claim
39 words
A memory device according to claim 31, wherein said bipolar transistor comprises a base region of said first conductivity type, formed in said well region of said second conductivity type, and an emitter region of said second conductivity type.
Claim 38
Dependent Claim
58 words
A memory device according to claim 32, wherein said bipolar transistor causes a parasitic bipolar transistor to appear in the memory device, which parasitic bipolar transistor creates minority carriers which act to destroy the information, the first buried layer and the further semiconductor region together acting as a shield to minority carriers caused by said parasitic bipolar transistor.
Claim 39
Dependent Claim
34 words
A memory device according to claim 25, further comprising: a semiconductor region, of said second conductivity type, wherein said semiconductor region is provided under said first buried layer and contacts said further semiconductor region.
Claim 40
Dependent Claim
140 words
A memory device comprising: a semiconductor substrate of a P-type conductivity; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a semiconductor region of N-type conductivity, opposite to said P-type conductivity, provided under said first buried layer, wherein said first buried layer and said semiconductor region are provided under the entire area where said memory array is formed.
Claim 41
Dependent Claim
140 words
A memory device comprising: a semiconductor substrate of a P-type conductivity; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a memory array formed on said main surface of said semiconductor layer and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a semiconductor region of N-type conductivity, opposite to said P-type conductivity, provided under said first buried layer, wherein said first buried layer and said semiconductor region are provided under the entire area where said memory array is formed.
Claim 42
Dependent Claim
49 words
A memory device according to claim 25, further comprising: a peripheral circuit including a bipolar transistor, formed on said main surface of said semiconductor layer, wherein said peripheral circuit is formed on said main surface of said semiconductor layer adjacent to the area where said memory array is formed.
Claim 43
Dependent Claim
24 words
A memory device according to claim 36, wherein said peripheral circuit further includes a MOSFET formed on said main surface of said semiconductor layer.
Claim 44
Dependent Claim
39 words
A memory device according to claim 37, further comprising: a second buried layer of said N-type conductivity, wherein said second buried layer is provided under said peripheral circuit and is disposed between said semiconductor substrate and said semiconductor layer.
Claim 45
Dependent Claim
55 words
A memory device according to claim 36, further comprising: a further semiconductor region of said N-type conductivity, formed in said semiconductor layer between said memory array and said bipolar transistor of said peripheral circuit, wherein said further semiconductor region contacts said first semiconductor region and extends up to the main surface of said semiconductor layer.
Claim 46
Dependent Claim
33 words
A memory device according to claim 39, wherein said semiconductor region provided under said first buried layer, together with said further semiconductor region, surrounds both said memory array and said first buried layer.
Claim 47
Dependent Claim
172 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a first semiconductor region formed in said semiconductor layer, said first semiconductor region extending up to the main surface of said semiconductor layer, wherein said first semiconductor region formed in said semiconductor layer divides said main surface of said semiconductor layer into a first area and a second area; a memory array formed on said main surface of said semiconductor layer in said first area and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a bipolar transistor formed on said main surface of said semiconductor layer in said second area.
Claim 48
Dependent Claim
172 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a first semiconductor region formed in said semiconductor layer, said first semiconductor region extending up to the main surface of said semiconductor layer, wherein said first semiconductor region formed in said semiconductor layer divides said main surface of said semiconductor layer into a first area and a second area; a memory array formed on said main surface of said semiconductor layer in said first area and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a bipolar transistor formed on said main surface of said semiconductor layer in said second area.
Claim 49
Dependent Claim
17 words
A memory device according to claim 41, wherein said first semiconductor region contacts said first buried layer.
Claim 50
Dependent Claim
45 words
A memory device according to claim 42, wherein said first semiconductor region, together with said first buried layer, acts as a shield so as to prevent minority carriers in said semiconductor substrate and said semiconductor layer from entering said memory array and destroying said information.
Claim 51
Dependent Claim
20 words
A memory device according to claim 42, wherein said first semiconductor region extends so as to surround said memory array.
Claim 52
Dependent Claim
44 words
A memory device according to claim 42, wherein the memory cells include a switching MOSFET, wherein said first buried layer is provided under the switching MOSFET, and wherein said first buried layer acts to prevent a depletion layer from spreading beneath said switching MOSFET.
Claim 53
Dependent Claim
23 words
A memory device according to claim 45, wherein said buried layer is positioned such that said depletion layer reaches to said buried layer.
Claim 54
Dependent Claim
53 words
A memory device according to claim 42, further comprising: a second buried layer, of a second conductivity type, opposite to said first conductivity type, provided under at least said bipolar transistor, wherein said bipolar transistor is formed in a well region of said second conductivity type which is formed in said semiconductor layer.
Claim 55
Dependent Claim
29 words
A memory device according to claim 47, wherein a collector region of said bipolar transistor comprises said well region of said second conductivity type and said second buried layer.
Claim 56
Dependent Claim
39 words
A memory device according to claim 47, wherein said bipolar transistor comprises a base region of said first conductivity type, formed in said well region of said second conductivity type, and an emitter region of said second conductivity type.
Claim 57
Dependent Claim
60 words
A memory device according to claim 49, wherein said bipolar transistor causes a parasitic bipolar transistor to appear in the memory device, which parasitic bipolar transistor creates minority carriers which act to destroy the information, and wherein the first buried layer and the first semiconductor region together act as a shield to minority carriers created by said parasitic bipolar transistor.
Claim 58
Dependent Claim
36 words
A memory device according to claim 42, further comprising: a second semiconductor region, of said second conductivity type, wherein said second semiconductor region is provided under said first buried layer and contacts said first semiconductor region.
Claim 59
Dependent Claim
34 words
A memory device according to claim 51, wherein said second semiconductor region provided under said first buried layer, together with said first semiconductor region, surrounds both said memory array and said first buried layer.
Claim 60
Dependent Claim
24 words
A memory device according to claim 42, further comprising: a peripheral circuit having a MOSFET, formed on said main surface in said second area.
Claim 61
Dependent Claim
23 words
A memory device according to claim 53, wherein said peripheral circuit includes a composite circuit comprised of said bipolar transistor and said MOSFET.
Claim 62
Dependent Claim
30 words
A memory device according to claim 54, wherein said composite circuit is a word driver circuit for selecting predetermined memory cells from among said memory cells of said memory array.
Claim 63
Dependent Claim
264 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said semiconductor layer, said first semiconductor region extending up to the main surface f said semiconductor layer, wherein said first semiconductor region formed in said semiconductor layer divides said main surface of said semiconductor layer into a first area and a second area; a memory array formed on said main surface of said semiconductor layer in said first area and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a peripheral circuit including a plurality of input protective elements, formed on said main surface of said semiconductor layer in said second area; a second buried layer provided under said input protective elements and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a second semiconductor region of said second conductivity type provided under said second buried layer; wherein said first semiconductor region contacts said second semiconductor region.
Claim 64
Dependent Claim
264 words
A memory device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer on said semiconductor substrate, the semiconductor layer having a main surface; a first semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in said semiconductor layer, said first semiconductor region extending up to the main surface f said semiconductor layer, wherein said first semiconductor region formed in said semiconductor layer divides said main surface of said semiconductor layer into a first area and a second area; a memory array formed on said main surface of said semiconductor layer in said first area and including a plurality of MOS memory cells, the memory cells being adapted to hold information; a first buried layer provided under said memory array and being disposed between said semiconductor substrate and said semiconductor layer, said first buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; a peripheral circuit including a plurality of input protective elements, formed on said main surface of said semiconductor layer in said second area; a second buried layer provided under said input protective elements and being disposed between said semiconductor substrate and said semiconductor layer, said second buried layer being of the same conductivity type as that of said semiconductor substrate and having an impurity concentration higher than that of said semiconductor substrate; and a second semiconductor region of said second conductivity type provided under said second buried layer; wherein said first semiconductor region contacts said second semiconductor region.
Claim 65
Dependent Claim
64 words
A memory device according to claim 56, wherein said input protective elements create minority carriers in said semiconductor layer, which act to destroy the information, and wherein said first semiconductor region, together with said second semiconductor region, acts as a shield so as to prevent minority carriers in said semiconductor layer from entering said memory array in said first area and destroying said information.
Claim 66
Dependent Claim
68 words
A memory device according to claim 57, wherein said peripheral circuit includes a bipolar transistor, wherein said bipolar transistor causes a parasitic bipolar transistor to appear in the memory device, which parasitic bipolar transistor creates minority carriers which act to destroy the information, and wherein the first buried layer and the first semiconductor region together act as a shield to minority carriers created by said parasitic bipolar transistor.
Claim 67
Dependent Claim
39 words
A memory device according to claim 56, wherein said memory cells include a switching MOSFET and said peripheral circuit includes a bipolar transistor, and wherein said first semiconductor region is disposed between said switching MOSFET and said bipolar transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |