Patent US5147813A successfully refreshed from Google Patents.
US5147813A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Erase performance improvement via dual floating gate processing
Assignee: Intel Corp
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Filing: 1991-10-29
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Granted: 1992-09-15
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Expires: 2011-10-29
Abstract
Abstract A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 Å thickness. The second layer is a silicon dioxide layer of approximately 20-30 Å. The third layer is polysilicon of approximately 1000-1500 Å thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.
Inventors
- 👤 Been-Jon Woo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:03
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035; Y; Y10; Y10S; Y10S148/00; Y10S148/109; Y10S438/00; Y10S438/914; Y10S438/923
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
117 words
A process for forming a non-volatile memory cell which includes a control gate, a floating gate for storage of electrical charge, an intergate dielectric layer between said control gate and said floating gate, a substrate, and a tunnel oxide between said floating gate and said substrate wherein said floating gate is formed over said tunnel oxide by a method comprising the steps of: depositing a first polysilicon layer over said tunnel oxide; forming an insulative layer over said first polysilicon layer; depositing a second polysilicon layer over said insulative layer; and introducing a dopant into said second polysilicon layer to form said floating gate comprising said first polysilicon layer, said insulative layer and said second polysilicon layer.
Claim 2
Dependent Claim
117 words
A process for forming a non-volatile memory cell which includes a control gate, a floating gate for storage of electrical charge, an intergate dielectric layer between said control gate and said floating gate, a substrate, and a tunnel oxide between said floating gate and said substrate wherein said floating gate is formed over said tunnel oxide by a method comprising the steps of: depositing a first polysilicon layer over said tunnel oxide; forming an insulative layer over said first polysilicon layer; depositing a second polysilicon layer over said insulative layer; and introducing a dopant into said second polysilicon layer to form said floating gate comprising said first polysilicon layer, said insulative layer and said second polysilicon layer.
Claim 3
Dependent Claim
25 words
The process as defined in claim 1 wherein said process further comprises diffusing said dopant from said second polysilicon layer into said first polysilicon layer.
Claim 4
Dependent Claim
12 words
The process as defined in claim 2 wherein said dopant comprises phosphorus.
Claim 5
Dependent Claim
37 words
The process as defined in claim 3 wherein said dopant is implanted at an energy in the range of 20-40 KeV to a dose in the range of 1×10 14 ions/cm 2 -8×10 14 ions/cm 2 .
Claim 6
Dependent Claim
37 words
The process as defined in claim 4 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 7
Dependent Claim
37 words
The process as defined in claim 2 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 8
Dependent Claim
37 words
The process as defined in claim 3 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 9
Dependent Claim
12 words
The process as defined in claim 1 wherein said dopant comprises phosphorus.
Claim 10
Dependent Claim
37 words
The process as defined in claim 8 wherein said dopant is implanted at an energy in the range of 20-40 keV to a dose in the range of 1×10 14 ions/cm 2 -8×10 14 ions/cm 2 .
Claim 11
Dependent Claim
37 words
The process as defined in claim 9 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 12
Dependent Claim
37 words
The process as defined in claim 8 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 13
Dependent Claim
37 words
The process as defined in claim 1 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 14
Dependent Claim
23 words
The process as defined in one of claims 1-12 wherein the thickness of said insulative layer is in the range of 15-50 Å.
Claim 15
Dependent Claim
14 words
The process as defined in claim 13 wherein said insulative layer comprises silicon dioxide.
Claim 16
Dependent Claim
58 words
The method of claim 1 wherein said dopant is introduced into said first polysilicon layer by diffusion of said dopant from said second polysilicon layer through said insulative layer into said first polysilicon layer, said insulative layer being sufficiently thin so as to allow said dopant to pass from said second polysilicon layer to said first polysilicon layer.
Claim 17
Dependent Claim
91 words
A process for forming a non-volatile memory cell which includes a floating gate for storage of electrical charge wherein said floating gate is formed by a method comprising the steps of: depositing a first polysilicon layer over a tunnel oxide; forming an insulative layer in the range of 15-50 Å over said first polysilicon layer; depositing a second polysilicon layer over said insulative layer; and introducing a dopant into said second polysilicon layer to form said floating gate comprising said first polysilicon layer, said insulative layer and said second polysilicon layer.
Claim 18
Dependent Claim
91 words
A process for forming a non-volatile memory cell which includes a floating gate for storage of electrical charge wherein said floating gate is formed by a method comprising the steps of: depositing a first polysilicon layer over a tunnel oxide; forming an insulative layer in the range of 15-50 Å over said first polysilicon layer; depositing a second polysilicon layer over said insulative layer; and introducing a dopant into said second polysilicon layer to form said floating gate comprising said first polysilicon layer, said insulative layer and said second polysilicon layer.
Claim 19
Dependent Claim
57 words
The method of claim 16 wherein said dopant is introduced into said first polysilicon layer by diffusion of said dopant from said second polysilicon layer through said insulative layer into said first polysilicon layer, said insulative being sufficiently thin so as to allow said dopant to pass from said second polysilicon layer to said first polysilicon layer.
Claim 20
Dependent Claim
70 words
A process for forming a floating gate for a non-volatile memory cell comprising the steps of: depositing a first polysilicon layer over a tunnel oxide; forming an insulative layer over said first polysilicon layer; depositing a second polysilicon layer over said insulative layer; and introducing a dopant into said second polysilicon layer to form said floating gate comprising said first polysilicon layer, said insulative layer and said second polysilicon layer.
Claim 21
Dependent Claim
70 words
A process for forming a floating gate for a non-volatile memory cell comprising the steps of: depositing a first polysilicon layer over a tunnel oxide; forming an insulative layer over said first polysilicon layer; depositing a second polysilicon layer over said insulative layer; and introducing a dopant into said second polysilicon layer to form said floating gate comprising said first polysilicon layer, said insulative layer and said second polysilicon layer.
Claim 22
Dependent Claim
25 words
The process as defined in claim 18 wherein said process further comprises diffusing said dopant from said second polysilicon layer into said first polysilicon layer.
Claim 23
Dependent Claim
37 words
The process as defined in claim 19 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 24
Dependent Claim
37 words
The process as defined in claim 18 wherein the thickness of said first polysilicon layer is in the range of 200-700 Å and the thickness of said second polysilicon layer is in the range of 800-2000 Å.
Claim 25
Dependent Claim
23 words
The process as defined in one of claims 18-20 wherein the thickness of said insulative layer is in the range of 15-50 Å.
Claim 26
Dependent Claim
14 words
The process as defined in claim 22 wherein said insulative layer comprises silicon dioxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |