Grouping device for forming input signals into groups

Claim 2

A grouping device for forming n input signals into m groups, wherein both n and m are greater than zero, comprising: a register table having m registers corresponding to m groups, each register including an n-bits data storing portion, each bit of said data storing portion corresponding to one of said n input signals, wherein when data is stored in said data storing portion each bit of said data stored in said data storing portion designates an assignment of one of said n-input signals to one of said m groups; a grouping means receiving said n input signals and grouping signals output from each of said registers in said register table, each of said grouping signals indicating whether said data designating an assignment is presently stored in said data storing portion of the register, wherein said grouping means comprises m converter circuits, each of said converter circuits receiving said n input signals and n grouping signals output from one of said m registers, said grouping means selecting one group from said m groups for each input signal and grouping said each input signal into said selected group depending on which of said m-registers data corresponding to said each input signal is stored in.

Claim 3

A grouping device as claimed in claim 1, wherein n is equal to m.

Claim 4

A grouping device as claimed in claim 1, further comprising a CPU and means for supplying register data, a writing signal and a selecting signal output from said CPU to said registers, wherein the contents of said each register are changed when said register data, said writing signal and said selecting signal output from said CPU are received thereby.

Claim 5

A grouping device as claimed in claim 1, further comprising a CPU and means for supplying register data, a writing signal and a selecting signal output from said CPU to said registers, wherein said each register comprises n register circuits, and said each register circuit receives said register data, said writing signal and said selecting signal from said CPU and outputs a grouping signal.

Claim 6

A grouping device as claimed in claim 4, wherein said each register circuit comprises: a latch circuit including a first inverter and a register-type inverter cross-connected therebetween; an inverter circuit having a transmission gate for ON/OFF switching when receiving said writing signal and an inverted writing signal through a second inverter, an output of said inverter circuit being connected to an input of said latch circuit; and a logic circuit, including a third inverter, first and second AND-gates, and an OR-gate, an input of said third inverter being supplied with register data and an output of said third inverter being connected to an input of said first AND-gate, another input of said first AND-gate being connected to an output of said latch circuit, inputs of said second AND-gates being supplied with said register data and said selecting signal, and outputs of said first and second AND-gates being applied to inputs of said OR-gate.

Claim 7

A grouping device as claimed in claim 1, wherein said each converter circuit comprises one n-inputs OR-gate and n AND-gates corresponding to a total number of said input signals, the n inputs of said each OR-gate being supplied with output signals of said n AND-gates, respectively.

Claim 8

An interrupt controller for grouping n interrupt requests output from n input-output units into m interrupt levels of a CPU, wherein both n and m are greater than zero, comprising: a register table having m registers corresponding to said m interrupt levels, each register including an n-bits data storing portion, each bit of said data storing portion corresponding to one of said n interrupt requests, wherein when data is stored in said data storing portion each bit of said data stored in said data storing portion designates an assignment of one of said n interrupt request to one of said m interrupt levels of said CPU; and a grouping means receiving said n interrupt requests and grouping signals output from each of said registers in said register table, each of said grouping signals indicating whether said data designating said assignment is presently stored in said data storing portion of the register, wherein said grouping means comprises m converter circuits, each of said converter circuits receiving said n interrupt requests output from said n input-output units and n grouping signals output from said each register, said grouping means selecting one interrupt level from said m interrupt levels of said CPU for each interrupt request and grouping said each interrupt request into said selected interrupt level depending on which of said m-registers data corresponding to said each interrupt request is stored in.

Claim 9

An interrupt controller for grouping n interrupt requests output from n input-output units into m interrupt levels of a CPU, wherein both n and m are greater than zero, comprising: a register table having m registers corresponding to said m interrupt levels, each register including an n-bits data storing portion, each bit of said data storing portion corresponding to one of said n interrupt requests, wherein when data is stored in said data storing portion each bit of said data stored in said data storing portion designates an assignment of one of said n interrupt request to one of said m interrupt levels of said CPU; and a grouping means receiving said n interrupt requests and grouping signals output from each of said registers in said register table, each of said grouping signals indicating whether said data designating said assignment is presently stored in said data storing portion of the register, wherein said grouping means comprises m converter circuits, each of said converter circuits receiving said n interrupt requests output from said n input-output units and n grouping signals output from said each register, said grouping means selecting one interrupt level from said m interrupt levels of said CPU for each interrupt request and grouping said each interrupt request into said selected interrupt level depending on which of said m-registers data corresponding to said each interrupt request is stored in.

Claim 10

An interrupt controller as claimed in claim 7, wherein n is equal to m.

Claim 11

An interrupt controller as claimed in claim 7, further comprising means for supplying register data, a writing signal and a selecting signal output from said CPU to said registers, wherein the contents of said each register are changed when said register data, said writing signal and said selecting signal output from said CPU are received thereby.

Claim 12

An interrupt controller as claimed in claim 7, further comprising means for supplying register data, a writing signal and a selecting signal output from said CPU to said registers, wherein said each register comprises n register circuits, and said each register circuit receives said register data, said writing signal and said selecting signal from said CPU and outputs a grouping signal.

Claim 13

An interrupt controller as claimed in claim 10, wherein said each register circuit comprises: a latch circuit including a first inverter and a register-type inverter cross-connected therebetween; an inverter circuit having a transmission gate for ON/OFF switching when receiving said writing signal and an inverted writing signal through a second inverter, an output of said inverter circuit being connected to an input of said latch circuit; and a logic circuit including a third inverter, first and second AND-gates, and an OR-gate, an input of said third inverter being supplied with register data and an output of said third inverter being connected to an input of said first AND-gate, another input of said first AND-gate being connected to an output of said latch circuit, inputs of said second AND-gates being supplied with said register data and said selecting signal, and outputs of said first and second AND-gates being applied to inputs of said OR-gate.

Claim 14

An interrupt controller as claimed in claim 7, wherein said each converter circuit comprises one n-inputs OR-gate and n AND-gates corresponding to a total number of said interrupt requests, the n-inputs of said each OR-gate being supplied with output signals of said n AND-gates.