I/O Control system having a plurality of access enabling bits for controlling access to selective ports of an I/O device

Claim 2

A digital computer apparatus for controlling direct access to an input/output (I/O) device comprising: a central processing unit (CPU) for performing a plurality of substantially simultaneous tasks; a plurality of I/O ports coupled to said CPU, for accessing I/O devices; means for accessing a plurality of I/O access enabling bits stored in a first storage means coupled to said CPU, said plurality of I/O access enabling bits being associated with said plurality of I/O ports, wherein for each task a corresponding I/O access enabling bit is assigned for each I/O port and in which a value of said corresponding I/O access enabling bit determines accessibility of its associated I/O port by that task, said plurality of I/O access enabling bits being stored in a variable length storage location; means for selecting a plurality of said I/O access enabling bits for each task, said plurality of I/O access enabling bits selected by said means for selecting corresponding to I/O ports of said I/O device, said means for selecting being coupled to said CPU and to said first storage means; control means for permitting a given task to directly access said I/O device when said corresponding plurality of I/O access enabling bits selected by said means for selecting are of a first value and prohibiting access when said corresponding plurality of I/O access enabling bits selected by said means for selecting are of a second value, such that an I/O instruction for directly accessing an I/O port of said I/O device is permitted, only if said corresponding I/O access enabling bit for a corresponding task is of a first value, said control means being coupled to said CPU and to said means for accessing.

Claim 3

The apparatus as defined in claim 1, wherein said control means further comprises a means for modifying a CPU instruction for accessing said I/O port when said access enabling bit is of said second value.

Claim 4

The apparatus as defined in claim 2, further including second storage means coupled to said control means, said second storage means for storing a set of modifying instructions and generating said modifying instruction when said corresponding I/O access enabling bit is of said second value.

Claim 5

The apparatus as defined in claim 3, wherein said variable length storage locations of said first storage means are bit mapped to store said I/O access enabling bits.

Claim 6

The apparatus as defined in claim 4, wherein said first storage means is programmable.

Claim 7

The apparatus as defined in claim 5, wherein said set of modifying instructions in said second storage means is programmable.

Claim 8

The apparatus as defined in claim 6, wherein said access enabling bit identified with its port for said given task is comprised of a single bit such that said first value is a 0 (zero) and said second value is a 1 (one).

Claim 9

The apparatus as defined in claim 7, wherein said CPU and said modifying instructions access a plurality of contiguous ports.

Claim 10

The apparatus according to claim 1 wherein said control means is implemented in microcode.

Claim 11

A digital computer apparatus for selectively controlling direct access to an input/output (I/O) device comprising: a central processing unit (CPU) for performing a plurality of substantially simultaneous tasks; a plurality of I/O ports coupled to said CPU for accessing I/O devices; means for accessing a plurality of I/O access enabling bits stored in a first memory coupled to said CPU, said plurality of I/O access enabling bits being associated with said plurality of I/O ports, wherein for each task, a corresponding I/O access enabling bit is assigned for each I/O port and in which a value of said corresponding I/O access enabling bit determines accessibility of its associated I/O port by that task, said plurality of I/O access enabling bits being stored in a variable length storage location; means for accessing a set of modifying instructions stored in a second memory coupled to said CPU; means for selecting a plurality of said I/O access enabling bits for each task, said plurality of I/O access enabling bits selected by said means for selecting corresponding to I/O ports of said I/O device, said means for selecting being coupled to said CPU and to said first memory; control means for permitting a given task to directly access said I/O device when said corresponding plurality of I/O access enabling bits selected by said means for selecting are of a first value and providing an instruction from said set of modifying instructions to virtualize access to said I/O device when said plurality of I/O access enabling bits selected by said means for selecting are of a second value, said control means being coupled to said CPU, said means for accessing said first memory and said means for accessing said second memory being coupled to said control means,

Claim 12

A digital computer apparatus for selectively controlling direct access to an input/output (I/O) device comprising: a central processing unit (CPU) for performing a plurality of substantially simultaneous tasks; a plurality of I/O ports coupled to said CPU for accessing I/O devices; means for accessing a plurality of I/O access enabling bits stored in a first memory coupled to said CPU, said plurality of I/O access enabling bits being associated with said plurality of I/O ports, wherein for each task, a corresponding I/O access enabling bit is assigned for each I/O port and in which a value of said corresponding I/O access enabling bit determines accessibility of its associated I/O port by that task, said plurality of I/O access enabling bits being stored in a variable length storage location; means for accessing a set of modifying instructions stored in a second memory coupled to said CPU; means for selecting a plurality of said I/O access enabling bits for each task, said plurality of I/O access enabling bits selected by said means for selecting corresponding to I/O ports of said I/O device, said means for selecting being coupled to said CPU and to said first memory; control means for permitting a given task to directly access said I/O device when said corresponding plurality of I/O access enabling bits selected by said means for selecting are of a first value and providing an instruction from said set of modifying instructions to virtualize access to said I/O device when said plurality of I/O access enabling bits selected by said means for selecting are of a second value, said control means being coupled to said CPU, said means for accessing said first memory and said means for accessing said second memory being coupled to said control means,

Claim 13

The apparatus as defined in claim 10, wherein said control means further comprises a programmable logic array having a set of controlling instructions.

Claim 14

The apparatus as defined in claim 11, wherein said variable length storage locations of said first memory are bit mapped to store said access enabling bits.

Claim 15

The apparatus as defined in claim 12, wherein said set of modifying instructions in said second memory is programmable.

Claim 16

The apparatus as defined in claim 13, wherein said CPU and said modifying instructions access a plurality of contiguous ports.

Claim 17

The apparatus as defined in claim 10, wherein said control means further includes a programmable memory on a semiconductor device.

Claim 18

The apparatus according to claim 10 wherein said control means is implemented in microcode.

Claim 19

In a digital computer apparatus having a central processing unit (CPU), means for performing a plurality of substantially simultaneous tasks, and a plurality of I/O ports coupled to said CPU, for accessing I/O devices, a process for controlling access to an I/O device, comprising the steps of: receiving an I/O request instruction for accessing said I/O device by one of said plurality of substantially simultaneous tasks; selecting a plurality of I/O access enabling bits for each task, said selected plurality of I/O access enabling bits corresponding to I/O ports of said I/O device, said plurality of I/O access enabling bits being stored in a storage means; permitting access of said selected I/O device by said one of said plurality of substantially simultaneous tasks if said selected plurality of I/O access enabling bits are of a first value; and prohibiting access of said selected I/O device by said one of said plurality of substantially simultaneous tasks if said selected plurality of I/O access enabling bits are of a second value.

Claim 20

In a digital computer apparatus having a central processing unit (CPU), means for performing a plurality of substantially simultaneous tasks, and a plurality of I/O ports coupled to said CPU, for accessing I/O devices, a process for controlling access to an I/O device, comprising the steps of: receiving an I/O request instruction for accessing said I/O device by one of said plurality of substantially simultaneous tasks; selecting a plurality of I/O access enabling bits for each task, said selected plurality of I/O access enabling bits corresponding to I/O ports of said I/O device, said plurality of I/O access enabling bits being stored in a storage means; permitting access of said selected I/O device by said one of said plurality of substantially simultaneous tasks if said selected plurality of I/O access enabling bits are of a first value; and prohibiting access of said selected I/O device by said one of said plurality of substantially simultaneous tasks if said selected plurality of I/O access enabling bits are of a second value.

Claim 21

The method defined by claim 17 further including the step of modifying said I/O request instruction when said I/O access enabling bit is of a second value, such that a different I/O request instruction is generated.

Claim 22

The method defined by claim 18, wherein said first value is a 0 (zero) and said second value is a 1 (one).