A multiprocessor resource locking system and its method of operation

Claim 2

A multiprocessor resource locking system including a plurality of actual processors sharing a common resource and having at least one lock having a plurality of possible actual states, said system including transition table means (10) for storing the lock state transition information including a plurality of first lock states and requests which may occur in each of said plurality of first lock states and a second lock state which will result for a given combination of first lock state and request, characterized in that said first and second lock states comprises canonical states expressed in terms of canonical processors and each representing a plurality of different actual lock states, and that the system further comprises mapping means (18) for mapping canonical processors in said transition table to actual processors.

Claim 3

A system as defined in Claim 1, wherein the transition table means includes actual-canonical conversion means (12) for receiving a processor identification code ( PK ) designating the source of a received request and for converting said processor identification code in accordance with the mapping of canonical processors to actual processors in order to obtain a canonical processor identification code (CPk').

Claim 4

A system as defined in Claim 1, wherein the transition table means further comprises means (17) for providing a new canonical state vector (CSi') in accordance with a combination of a request identification code ( R j) designating a particular received request, an original state vector (CSi) representing the state of said lock upon receiving said request, and said canonical processor identification code (CPk').

Claim 5

A system ss defined in Claim 3, further comprising means (17) for generating a permutation vector (CCM) in accordance with said address input, said transition table means further comprising map conversion means (18) for converting said first canonical-actual map to a second canonical-atual map in accordance with said permutation vector (CCM).

Claim 6

A system as defined in Claim 3, further comprising means responsive to said address for generating a notify vector designating the canonical processors to be notified of said second lock state, said transition tablemeans further comprising mapping means responsive to said notify vector and to said canonical-actual map for generating an output signal representing the physical processors to be notified.

Claim 9

A method as defined in Claim 6, wherein said maintaining step comprises the steps of: generating a first CAM corresponding to a first lock state, generating a canonical-canonical map CCM in accordance with said given combination; and changing said CAM to a new CAM in accordance with said CCM.

Claim 10

A method as defined in Claim 6, further comprising the step of generating a notify vector representing canonical processors to be notified of a transition from a first state to a second state; and combining said notify vector and said CAM to determine the actual processors to be notified.

Claim 11

A method as defined in Claim 6, further comprising the steps of: receiving a request Rj against said lock L from a processor PK; determining the current state (CSi, CAM) of said lock L, where CSi represents a canonical lock states in which one of said first actual lock states is represented in terms of canonical processors, and CAM is a canonical-actual map indicating the correspondence between canonical and actual processors; generating a canonical processor identification code CPk' defined by CAM(CPk')=Pk; determining a transition table vector T(i, j, k') = (CSi', CCM), wherein CSi' represents a second canonical state and CCM represents a canonical-canonical map indicating changes to be made to said CAM accociated with transition from a first actual lock state to a second actual lock state; generating a new canonical-atual map CAM' in accordance with a combination of said CAM and CCM; and setting the state of said lock L to a second lock state given by (CSi', CAM').

Claim 12

A method as defined in Claim 9, further comprising the step of generating a canonical notify vector representing the canonical processors to be notified of a transition from a first state to a second state; converting said canonical notify vector to an actual notify vector in accordance with said original CAM; and notifying selected processors in accordance with said actual notify vector.