Single chip gate array

Claim 1

A gate array semiconductor single chip integrated circuit, comprising: a memory cell array having a plurality of word lines and a plurality of bit lines in matrix form; an x-address decoder for the word lines of said memory cell array and functioning as x-select means; a data register coupled to said memory cell array; a gate array unit having basic cells and being coupled to said data register; application specific mask pattern layer means for wiring said basic cells in a specific application manner, including forming a part of y select means for providing selective signals; sense amplifier means coupled between said memory cell array and said data register for detecting and amplifying particular signal levels on said bit lines of said memory cell array and passing amplified signals to said data register; coupling means between said data register and said gate array unit, and said coupling means having a group of data signal lines corresponding to said bit lines; switch circuit means coupled between basic cells of said gate array unit and said data register and responsive to the selective signals for selecting particular ones of said signal data lines to be used in the transfer of data between said data register and said gate array; and said switch circuit means and said gate array unit functioning as a y select circuit.

Claim 12

A method for producing a gate array semiconductor single chip integrated circuit, comprising the following steps performed on a single semiconductor chip: forming a standardized memory cell array having a plurality of memory cells, bit lines and word lines in the form of a matrix; forming an x-address decoder for the word lines of said memory cell array to function as x-select means; forming a gate array unit having a group of unconnected basic cells; forming a data register for the exchange of data between the gate array unit and the memory cell array; forming data signal lines between the data register and the gate array unit; and wiring the basic cells of the gate array unit by using an application specific individual mask pattern providing only the wiring, thereby forming at least a part of y select means, and forming a switch circuit in the gate array unit for selecting particular ones of the data signal lines for data transfer as a further part of the y select means.

Claim 13

A method for producing a gate array semiconductor single chip integrated circuit, comprising the following steps performed on a single semiconductor chip: forming a standardized memory cell array having a plurality of memory cells, bit lines and word lines in the form of a matrix; forming an x-address decoder for the word lines of said memory cell array to function as x-select means; forming a gate array unit having a group of unconnected basic cells; forming a data register for the exchange of data between the gate array unit and the memory cell array; forming data signal lines between the data register and the gate array unit; and wiring the basic cells of the gate array unit by using an application specific individual mask pattern providing only the wiring, thereby forming at least a part of y select means, and forming a switch circuit in the gate array unit for selecting particular ones of the data signal lines for data transfer as a further part of the y select means.