Patent US5460752A successfully refreshed from Google Patents.
Patent US5146157A successfully refreshed from Google Patents.
US5146157A
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Calculation apparatus for an electronic meter
Assignee: Actaris UK Ltd
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Filing: 1990-12-28
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Granted: 1992-09-08
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Expires: 2010-12-28
Abstract
Abstract Separate pulse inputs from respective metering circuits, representing the reactive R and in-phase W power components, are converted to a pulse output V representing the vector sum of those components. The two inputs are applied to increment respective registers, the output V is held in a third register, and a fourth register is provided to store the REMAINDER value (W 2 +R 2 )-(V+1) 2 . The meter includes a processor for incrementing the REMAINDER value by 2W+1 for each increment of W and 2R+1 for each increment of R and for incrementing V whenever the REMAINDER value is zero or positive and at the same time reducing the REMAINDER value by 2V 1 +1, where V 1 is the incremented value of V. The FRACTIONAL error in the value of V is determined by means of a look-up table.
Inventors
- 👤 David J. Clarke
- 👤 Michael D. Hutchinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:44
CPC Classifications
G; G01; G01R; G01R21/00; G01R21/133
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
188 words
Calculation apparatus for an electronic power meter comprising: (a) first means for receiving input pulses representing a reactive component, R from a first metering circuit; (b) second means for receiving input pulses representing an in-phase power component, W, from a second metering circuit; (c) means for processing said input pulses representing said reactive component, R, and said input pulses representing said in-phase power component, W, into a pulse output, V, representative of the vector sum of said input pulses, said means for processing comprising a first register for accumulating said input pulses R, a second register for accumulating said input pulses W, and a third register for retaining said output pulses V, and a fourth register which stores the remainder (W 2 +R 2 )-(V+1) 2 , said means for processing further comprising incrementing means for incrementing said remainder value by 2W+1 for each increment of W and 2R+1 for each increment of R, said incrementing means incrementing V whenever said remainder value is zero or positive and reducing the value of said remainder value by 2V 1 +1, where V 1 is the incremented value of V.
Claim 2
Dependent Claim
188 words
Calculation apparatus for an electronic power meter comprising: (a) first means for receiving input pulses representing a reactive component, R from a first metering circuit; (b) second means for receiving input pulses representing an in-phase power component, W, from a second metering circuit; (c) means for processing said input pulses representing said reactive component, R, and said input pulses representing said in-phase power component, W, into a pulse output, V, representative of the vector sum of said input pulses, said means for processing comprising a first register for accumulating said input pulses R, a second register for accumulating said input pulses W, and a third register for retaining said output pulses V, and a fourth register which stores the remainder (W 2 +R 2 )-(V+1) 2 , said means for processing further comprising incrementing means for incrementing said remainder value by 2W+1 for each increment of W and 2R+1 for each increment of R, said incrementing means incrementing V whenever said remainder value is zero or positive and reducing the value of said remainder value by 2V 1 +1, where V 1 is the incremented value of V.
Claim 3
Dependent Claim
37 words
The calculation apparatus of claim 1 in which V is reset to zero by said incrementing means, and the calculation of V is restarted whenever the value of R or W has increased by a predetermined count.
Claim 4
Dependent Claim
76 words
The calculation apparatus of claim 1 wherein said means for processing further comprises fractional error determining means for determining the fractional error in V comprising a look-up table which may be interrogated by incrementing means whenever the value of R or W has increased by a predetermined count, said look-up table providing said incrementing means with the frictional error in the vector sum corresponding to each value of W or R, respectively, less than that count.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-08 | 1996-03-09 | 1996-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-08 | 2000-03-09 | 2000-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-08 | 2004-03-09 | 2004-09-08 | $7700.00 | Window Closed / Lapsed |