Turn-on/off driving technique for insulated gate thyristor

Claim 2

A thyristor comprising: a first emitter layer of a first conductivity type; a first base layer of a second conductivity type; a second base layer of the first conductivity type; a second emitter layer of the second conductivity type, said first base layer having a first surface portion which is in lateral contact with said first emitter layer, and a second surface portion which is in lateral contact with said second base layer and separated from said second emitter layer by a layer portion of said second base layer which is positioned between said first base layer and said second emitter layer; a first electrode connected to said second emitter layer; a second electrode connected to said first emitter layer; a first gate electrode formed on said first surface portion of said first base layer; and a second gate electrode insulatively disposed above said second surface portion of said first base layer to form a voltage-controlled switching transistor together with said first base layer and said second emitter layer, said layer portion of said second base layer serving as a channel region of said transistor.

Claim 3

The thyristor according to claim 1, wherein said anode electrode is connected to both said second base layer and said second emitter layer.

Claim 4

The thyristor according to claim 2, wherein said first base layer comprises: a first semiconductive layer portion having said first surface portion; and a second semiconductive layer portion having said second surface portion, said second semiconductive layer being of a conductivity type the same as that of said first semiconductor layer portion and being larger in a resistivity than said second semiconductive layer.

Claim 5

The thyristor according to claim 3, wherein said first conductivity is an n conductivity type, whereas said second conductivity type is a p conductivity type.

Claim 6

The thyristor according to claim 2, wherein said first base layer comprises: a heavily doped semiconductive layer portion having said first surface portion, and a normally doped semiconductive layer portion having said second surface portion, said normally doped semiconductive layer portion being of the same conductivity type as said heavily doped semiconductive layer portion.

Claim 7

The thyristor according to claim 2, wherein said first base layer comprises: a normally doped semiconductive layer portion having said first surface portion, and a lightly doped semiconductive layer portion having said second surface portion, said lightly doped semiconductive layer being of the same conductivity type as said normally doped semiconductive layer portion.

Claim 8

A gate-turn off thyristor comprising: a first semiconductive layer of a first conductivity type serving as a first emitter; a second semiconductive layer of a second conductivity type having a resistance lower than a predetermined value; a third semiconductive layer of the second conductivity type being in direct contact with said second semiconductive layer, said third semiconductive layer having a resistance lower than the predetermined value, said second and third semiconductive layers serving as a first base; a fourth semiconductive layer of the first conductivity type serving as a second base; a fifth semiconductive layer of the second conductivity type serving as a second emitter, said second semiconductive layer having a first surface portion which is in lateral contact with said first semiconductive layer, said third semiconductive layer having a second surface portion which is in lateral contact with said fourth semiconductive layer and separated from said fifth semiconductive layer by a layer portion of said fourth semiconductive layer which is positioned between said third semiconductive layer and said fifth semiconductive layer; an anode electrode formed at least on said fifth semiconductive layer; a cathode electrode connected to said first semiconductive layer; a first gate electrode formed on said first surface portion; and a second gate electrode insulatively disposed above said second surface portion to form a metal-insulation-semiconductor field effect transistor using said layer portion of said fourth semiconductive layer as a channel region thereof.

Claim 9

A gate-turn off thyristor comprising: a first semiconductive layer of a first conductivity type serving as a first emitter; a second semiconductive layer of a second conductivity type having a resistance lower than a predetermined value; a third semiconductive layer of the second conductivity type being in direct contact with said second semiconductive layer, said third semiconductive layer having a resistance lower than the predetermined value, said second and third semiconductive layers serving as a first base; a fourth semiconductive layer of the first conductivity type serving as a second base; a fifth semiconductive layer of the second conductivity type serving as a second emitter, said second semiconductive layer having a first surface portion which is in lateral contact with said first semiconductive layer, said third semiconductive layer having a second surface portion which is in lateral contact with said fourth semiconductive layer and separated from said fifth semiconductive layer by a layer portion of said fourth semiconductive layer which is positioned between said third semiconductive layer and said fifth semiconductive layer; an anode electrode formed at least on said fifth semiconductive layer; a cathode electrode connected to said first semiconductive layer; a first gate electrode formed on said first surface portion; and a second gate electrode insulatively disposed above said second surface portion to form a metal-insulation-semiconductor field effect transistor using said layer portion of said fourth semiconductive layer as a channel region thereof.

Claim 10

The thyristor according to claim 7, further comprising: a sixth semiconductive layer of the first conductivity type formed in said fifth semiconductive layer, said anode electrode being connected to said sixth semiconductive layer.

Claim 11

The thyristor according to claim 8, wherein said sixth semiconductive layer is separated from said fourth semiconductive layer by a layer portion of said fifth semiconductive layer which is positioned between said fourth semiconductive layer and said sixth semiconductive layer and which is insulatively covered by said second gate layer thereby to form a second metal-insulation-semiconductor field effect transistor using said layer portion of said fifth semiconductive layer as a channel region thereof.

Claim 12

The thyristor according to claim 9, wherein said fifth semiconductive layer covers a surface of said fourth semiconductive layer which is positioned beneath said anode electrode.

Claim 13

The thyristor according to claim 8, further comprising: a seventh semiconductive layer of the first conductivity type formed in said second semiconductive layer to define a certain surface portion of said second semiconductive layer which is positioned between said first semiconductive layer and said seventh semiconductive layer; a third gate electrode insulatively disposed above said certain surface portion of said second semiconductive layer to form a third metal-insulation-semiconductor field effect transistor using said layer portion of said second semiconductive layer as a channel region thereof.

Claim 14

The thyristor according to claim 11, wherein said thyristor has a mesa structure.

Claim 15

The thyristor according to claim 11, wherein said second semiconductive layer has a heavily doped semiconductor layer of the second conductivity type.

Claim 16

The thyristor according to claim 11, wherein said second semiconductive layer has heavily doped semiconductor layers of the second conductivity type.

Claim 17

The thyristor according to claim 14, wherein said second and third semiconductive layers are made of a lightly doped semiconductive layer of the second conductivity type.

Claim 18

The thyristor according to claim 8, further comprising: a seventh semiconductive layer of the second conductivity type formed in said first semiconductive layer to define a certain surface portion of said first semiconductive layer which is positioned between said second semiconductive layer and said seventh semiconductive layer; a third gate electrode insulatively disposed above said certain surface portion of said first semiconductive layer to form a third metal-insulation-semiconductor field effect transistor using said certain surface portion of said first semiconductive layer as a channel region thereof.

Claim 19

The thyristor according to claim 16, wherein said thyristor has a mesa structure.