Thin-film transistor circuit

Claim 2

A thin-film transistor circuit comprising a main thin film transistor and two subsidiary thin film transistors, each of said main and subsidiary thin film transistors having respective source, drain and gate electrodes, wherein for each of said subsidiary thin film transistors, its respective gate electrode and one of its respective source and drain electrodes are coupled together and the other of said source and drain electrodes of each of said subsidiary thin film transistors are coupled together, each of said subsidiary thin film transistors having: a respective threshold voltage at which the respective subsidiary thin film transistor is rendered conducting when a first voltage of a first polarity exceeding said respective threshold voltage is applied to its respective gate electrode; and a respective channel region with a length selected for causing the respective subsidiary thin film transistor to break down when a second voltage of a polarity opposite to the first polarity and exceeding the threshold voltage of the other subsidiary thin film transistor is applied across the source and drain electrodes of the respective subsidiary thin film transistor; wherein said subsidiary thin film transistors are coupled between the gate electrode of said main thin film transistor and a reference potential so as to form an input protection device which causes a first of said subsidiary thin film transistors to conduct and a second of said subsidiary thin film transistors to break down when a third voltage exceeding said first voltage, is applied to the gate electrode of said main thin film transistor, and for causing said second subsidiary thin film transistor to conduct and said first subsidiary thin film transistor to break down when a fourth voltage having a polarity opposite to that of said third voltage and exceeding said first voltage is applied to the gate electrode of the main thin film transistor.

Claim 3

A thin-film transistor circuit according to claim 1, wherein the gate and drain electrodes of said second thin-film transistor are connected together and to the gate electrode of said first thin-film transistor and the gate and source electrodes said third thin-film transistor are connected together and to ground.

Claim 4

A thin-film transistor circuit according to claim 1 wherein each of said second and third thin-film transistors has a respective channel region length selected such that its break down voltage is in the range of from about 20 to about 30 volts.

Claim 5

A thin-film transistor circuit according to claim 1, wherein the channel region of each of said second and third thin-film transistors is formed of polycrystalline silicon and is bounded at each end by highly doped n conductivity type contact regions connecting with its source and drain electrodes.

Claim 6

A thin film transistor circuit according to claim 4, wherein the channel region of each of said second and third thin-film transistors is passivated by plasma hydrogenation.

Claim 7

A thin-film transistor circuit according to claim 1, wherein a plurality of main thin-film transistors are provided together with at least one input gate protection device.

Claim 8

A thin-film transistor circuit according to claim 6, wherein the main thin-film transistors are arranged in a matrix of rows and columns of main thin-film transistors with each row of main thin-film transistors having an input gate protection device.

Claim 9

A liquid crystal display device incorporating a thin-film transistor circuit in accordance with claim 1.

Claim 10

A thin-film transistor circuit according to claim 2, wherein each of said second and third thin-film transistors has a respective channel region length selected such that its break down voltage is in the range of from about 20 to about 30 volts.

Claim 11

A thin-film transistor circuit according to claim 2, wherein the channel region of each of said second and third thin-film transistors is formed of polycrystalline silicon and is bounded at each end by highly doped n conductivity type contact regions connecting with its source and drain electrodes.

Claim 12

A thin-film transistor circuit according to claim 3, wherein the channel region of each of said second and third thin-film transistors is formed of polycrystalline silicon and is bounded at each end by highly doped n conductivity type contact regions connecting with its source and drain electrodes.

Claim 13

A thin-film transistor circuit according to claim 9, wherein the channel region of each of said second and third thin-film transistors is formed of polycrystalline silicon and is bounded at each end by highly doped n conductivity type contact regions connecting with its source and drain electrodes.

Claim 14

A thin film transistor circuit according to claim 10, wherein the channel region of each of said second and third thin-film transistors is passivated by plasma hydrogenation.

Claim 15

A thin film transistor circuit according to claim 11, wherein the channel region of each of said second and third thin-film transistors is passivated by plasma hydrogenation.

Claim 16

A thin film transistor circuit according to claim 12, wherein the channel region of each of said second and third thin-film transistors is passivated by plasma hydrogenation.

Claim 17

A thin-film transistor circuit according to claim 5, wherein a plurality of main thin-film transistors are provided together with at least one input gate protection device.

Claim 18

A thin-film transistor circuit according to claim 15, wherein a plurality of main thin-film transistors are provided together with at least one input gate protection device.

Claim 19

A thin-film transistor circuit according to claim 5, wherein the main thin-film transistors are arranged in a matrix of rows and columns of main thin-film transistors with each row of main thin-film transistors having an input gate protection device.

Claim 20

A thin-film transistor circuit according to claim 17, wherein the main thin-film transistors are arranged in a matrix of rows and columns of main thin-film transistors with each row of main thin-film transistors having an input gate protection device.

Claim 21

A liquid crystal display device incorporating a thin-film transistor circuit in accordance with claim 19.

Claim 22

A thin film transistor circuit according to claim 1 wherein each of said second and third thin film transistors has a respective channel region length of from about 1.7 to 2.2 micrometers.

Claim 23

A liquid crystal display device comprising: a) a matrix of liquid crystal picture elements with each picture element having a picture electrode; b) a plurality of main thin film transistors each having first and second main electrodes and a gate electrode, the main thin film transistors being arranged in a matrix of rows and columns with each main thin film transistor having one main electrode connected to a respective picture electrode; c) a plurality of row conductors with each row conductor being connected to the gate electrode of each one of said main thin film transistors in a respective row of main thin film transistors; d) a plurality of column conductors with each column conductor being connected to the other main electrode of each of said main thin film transistors in a respective column of main thin film transistors; e) a row decoder/addressing circuit connected to each row conductor for causing the main thin film transistors in a selected row to become conducting; f) a column decoder/addressing circuit connected to each column conductor for allowing charge to be supplied to the main thin film transistors of a selected column which have been rendered conducting by the row decoder/addressing circuit; g) a plurality of input gate protection circuits, each coupled to a respective one of said row conductors and each comprising first and second subsidiary thin film transistors each having a source electrode, a drain electrode and a gate electrode, the gate electrode of said first subsidiary thin film transistor being connected to its drain electrode, the gate electrode of said second subsidiary thin film transistor being connected to its source electrode, and the source electrode of the said first subsidiary thin film transistor being connected to the drain electrode of said second subsidiary thin film transistor, each of said first and second thin film transistors having: a respective threshold voltage at which the respective subsidiary thin film transistor is rendered conducting when a first voltage of a first polarity exceeding said respective threshold voltage is applied to its respective gate electrode; and a respective channel region with a length selected for causing the respective subsidiary thin film transistor to break down when a second voltage of a polarity opposite to the first polarity and exceeding the threshold voltage of the other subsidiary thin film transistor is applied across the source and drain electrodes of the respective subsidiary thin film transistor; wherein said subsidiary thin film transistors are coupled between the gate electrode of said main thin film transistor and a reference potential so as to form an input protection device which causes a first of said subsidiary thin film transistors to conduct and a second of said subsidiary thin film transistors to break down when a third voltage exceeding said first voltage, is applied to the gate electrode of said main thin film transistor, and for causing said second subsidiary thin film transistor to conduct and said first subsidiary thin film transistor to break down when a fourth voltage having a polarity opposite to that of said third voltage and exceeding said first voltage is applied to the gate electrode of the main thin film transistor.

Claim 24

A liquid crystal display device comprising: a) a matrix of liquid crystal picture elements with each picture element having a picture electrode; b) a plurality of main thin film transistors each having first and second main electrodes and a gate electrode, the main thin film transistors being arranged in a matrix of rows and columns with each main thin film transistor having one main electrode connected to a respective picture electrode; c) a plurality of row conductors with each row conductor being connected to the gate electrode of each one of said main thin film transistors in a respective row of main thin film transistors; d) a plurality of column conductors with each column conductor being connected to the other main electrode of each of said main thin film transistors in a respective column of main thin film transistors; e) a row decoder/addressing circuit connected to each row conductor for causing the main thin film transistors in a selected row to become conducting; f) a column decoder/addressing circuit connected to each column conductor for allowing charge to be supplied to the main thin film transistors of a selected column which have been rendered conducting by the row decoder/addressing circuit; g) a plurality of input gate protection circuits, each coupled to a respective one of said row conductors and each comprising first and second subsidiary thin film transistors each having a source electrode, a drain electrode and a gate electrode, the gate electrode of said first subsidiary thin film transistor being connected to its drain electrode, the gate electrode of said second subsidiary thin film transistor being connected to its source electrode, and the source electrode of the said first subsidiary thin film transistor being connected to the drain electrode of said second subsidiary thin film transistor, each of said first and second thin film transistors having: a respective threshold voltage at which the respective subsidiary thin film transistor is rendered conducting when a first voltage of a first polarity exceeding said respective threshold voltage is applied to its respective gate electrode; and a respective channel region with a length selected for causing the respective subsidiary thin film transistor to break down when a second voltage of a polarity opposite to the first polarity and exceeding the threshold voltage of the other subsidiary thin film transistor is applied across the source and drain electrodes of the respective subsidiary thin film transistor; wherein said subsidiary thin film transistors are coupled between the gate electrode of said main thin film transistor and a reference potential so as to form an input protection device which causes a first of said subsidiary thin film transistors to conduct and a second of said subsidiary thin film transistors to break down when a third voltage exceeding said first voltage, is applied to the gate electrode of said main thin film transistor, and for causing said second subsidiary thin film transistor to conduct and said first subsidiary thin film transistor to break down when a fourth voltage having a polarity opposite to that of said third voltage and exceeding said first voltage is applied to the gate electrode of the main thin film transistor.