Multiple synchronized agile pulse generator

Claim 2

A multiple synchronized agile pulse generator, comprising: first logic means for providing a clock output; multifunction counter means connected to the first logic means for receiving the clock output therefrom and for providing first controlling outputs; first memory means for storing pulse width data; second memory means for storing pulse repetition interval data; the first and second memory means connected to the multifunction counter means for alternately applying the stored pulse width data and the stored pulse repetition interval data to the multifunction counter means, with said multifunction counter means providing the first controlling outputs in response to the clock output received thereby and to the pulse width and pulse repetition interval data applied thereto; second logic means connected to the multifunction counter means and responsive to the first controlling outputs therefrom for providing second controlling outputs; pattern counter means connected to the second logic means, with the second controlling outputs from the second logic means controlling the clocking rate of the pattern counter means, and said pattern counter means providing pulse pattern data; third memory means connected to the pattern counter means for storing the pulse pattern data therefrom; and means connected to the third memory means for accessing the stored pulse pattern data.

Claim 3

A pulse generator as described by claim 1, wherein: the first logic means is connected to an external signal source for receiving clock and trigger pulses therefrom and for providing the clock output in response thereto; and third logic means connected to an external command source for receiving commands therefrom, and connected to the first logic means for applying said commands thereto so that said first logic means provides the clock output.

Claim 4

A pulse generator as described by claim 2, including: a "start" function of the first logic means being initiated by a trigger pulse from the external signal source; a burst counter connected to the second logic means and responsive to a controlling output therefrom for providing an end-burst output and connected to the first logic means; fourth logic means connected to the pattern counter means and to the first logic means, said fourth logic means being responsive to an end of a data cycle of the pattern counter means for providing an end-cycle output; and a "stop" function of the first logic means being initiated by a trigger pulse from the external source, the end-burst output from the end-burst counter and the end-cycle output from the fourth logic means.

Claim 5

A pulse generator as described by claim 2, including: first sequencing counter means connected to the second logic means and to the first memory means; first sequencing register means connected to the first sequencing counter means for loading said first sequencing counter means; the first sequencing counter means being controlled by the second logic means for scanning the first memory means during a cycle of said first memory means, and for providing a terminal count at the completion of said cycle; and the first memory means connected to the second memory means, with the first memory means being responsive to the terminal count therefrom so that the data applied to the multifunction counter means is toggled from the first memory means to the second memory means.

Claim 6

A pulse generator as described by claim 4, including: a recycling counter connected to the first sequencing counter; a recycling register for loading the recycling counter; and the first sequencing counter controlling the recycling counter, whereupon the recycling counter provides a total count output indicating for how many pulse pattern groups a pulse repetition rate will remain unchanged.

Claim 7

A pulse generator as described by claim 5, including: a second sequencing counter connected to the recycling counter; a second sequencing register for loading the second sequencing counter; and the second sequencing counter being connected to the second memory means and responsive to the total count output from the recycling counter for enabling the second memory means to step to a next pulse repetition interval to be loaded in the multifunction counter means.

Claim 8

A pulse generator as described by claim 6, including: a pattern register connected to the pattern counter means for loading said pattern counter means; the pattern counter means being controlled by a controlling output from the second logic means and providing a terminal controlling output each time the multifunction counter means completes a cycle; and said pattern counter means being effective for scanning the third memory means.

Claim 9

A multiple synchronized agile pulse generator of the type responsive to externally provided clock, trigger and command signals, comprising: first logic means responsive to the externally provided clock, trigger and command signals for providing the clock output; second logic means receiving the externally provided command signals and connected to the first logic means for applying commands in response thereto to the first logic means so that said first logic means provides the clock output; multifunction counter means connected to the first logic means for receiving the clock output therefrom and for providing first controlling outputs; first memory means for storing pulse width data; second memory means for storing pulse repetition interval data; the first and second memory means connected to the multifunction counter means for alternately applying the stored pulse width data and the stored pulse repetition interval data to the multifunction counter means, with said multifunction counter means providing the first controlling outputs in response to the clock output received thereby and to the data applied thereto; third logic means connected to the multifunction counter means and responsive to the first controlling outputs therefrom for providing second controlling outputs; pattern counter means connected to the third logic means, with the second controlling outputs therefrom controlling the clocking rate of the pattern counter means, said pattern counter means providing pulse pattern data; third memory means connected to the pattern counter means for storing the pulse pattern data therefrom; and means connected to the third memory means for accessing the stored pulse pattern data.

Claim 10

A multiple synchronized agile pulse generator of the type responsive to externally provided clock, trigger and command signals, comprising: first logic means responsive to the externally provided clock, trigger and command signals for providing the clock output; second logic means receiving the externally provided command signals and connected to the first logic means for applying commands in response thereto to the first logic means so that said first logic means provides the clock output; multifunction counter means connected to the first logic means for receiving the clock output therefrom and for providing first controlling outputs; first memory means for storing pulse width data; second memory means for storing pulse repetition interval data; the first and second memory means connected to the multifunction counter means for alternately applying the stored pulse width data and the stored pulse repetition interval data to the multifunction counter means, with said multifunction counter means providing the first controlling outputs in response to the clock output received thereby and to the data applied thereto; third logic means connected to the multifunction counter means and responsive to the first controlling outputs therefrom for providing second controlling outputs; pattern counter means connected to the third logic means, with the second controlling outputs therefrom controlling the clocking rate of the pattern counter means, said pattern counter means providing pulse pattern data; third memory means connected to the pattern counter means for storing the pulse pattern data therefrom; and means connected to the third memory means for accessing the stored pulse pattern data.

Claim 11

A pulse generator as described by claim 8, including: a "start" function of the first logic means being initiated by a trigger pulse from the external signal source; a burst counter connected to the second logic means and responsive to a controlling output therefrom for providing an end-burst output and connected to the first logic means; fourth logic means connected to the pattern counter means and to the first logic means, said fourth logic means being responsive to an end of a data cycle of the pattern counter means for providing an end-cycle output; and a "stop" function of the first logic means being initiated by a trigger pulse from the external source, the end-burst output from the end-burst counter and the end-cycle output from the fourth logic means.

Claim 12

A pulse generator as described by claim 8, including: first sequencing counter means connected to the second logic means and to the first memory means; first sequencing register means connected to the first sequencing counter means for loading said first sequencing counter means; the first sequencing counter means being controlled by the third logic means for scanning the first memory means during a cycle of said first memory means, and for providing a terminal count at the completion of said cycle; and the first memory means connected to the second memory means, with the first memory means being responsive to the terminal count therefrom so that the data applied to the multifunction counter means is toggled from the first memory means to the second memory means.

Claim 13

A pulse generator as described by claim 10, including: a recycling counter connected to the first sequencing counter; a recycling register for loading the recycling counter; and the first sequencing counter controlling the recycling counter, whereupon the recycling counter provides a total count output indicating for how many pulse pattern groups a pulse repetition interval will remain unchanged.

Claim 14

A pulse generator as described by claim 11, including: a second sequencing counter connected to the recycling counter; a second sequencing register for loading the second sequencing counter; and the second sequencing counter being connected to the second memory means and responsive to the total count output from the recycling counter for enabling the second memory means to step to a next pulse repetition interval to be loaded in the multifunction counter means.

Claim 15

A pulse generator as described by claim 12, including: a pattern register connected to the pattern counter means for loading said pattern counter means; the pattern counter means being controlled by a controlling output from the third logic means and providing a terminal controlling output each time the multifunction counter means completes a cycle and; and said pattern counter means being effective for scanning the third memory means.

Claim 16

A multiple synchronized agile pulse generator, comprising: first means for providing first controlling outputs; first memory means for storing pulse width data; second memory means for storing pulse repetition interval data; the first and second memory means connected to the first means for alternately applying the stored pulse width data and the stored pulse repetition interval data thereto, with said first means providing the first controlling outputs in response to the applied data; second means connected to the first means and responsive to the first controlling outputs therefrom for providing second controlling outputs; pattern counter means connected to the second means, with the second controlling outputs controlling the clocking rate of the pattern counter means so that said pattern counter means provides pulse pattern data; third memory means connected to the pattern counter means for storing the pulse pattern data therefrom; and means connected to the third memory means for accessing the stored pulse pattern data.

Claim 17

A multiple synchronized agile pulse generator, comprising: first means for providing first controlling outputs; first memory means for storing pulse width data; second memory means for storing pulse repetition interval data; the first and second memory means connected to the first means for alternately applying the stored pulse width data and the stored pulse repetition interval data thereto, with said first means providing the first controlling outputs in response to the applied data; second means connected to the first means and responsive to the first controlling outputs therefrom for providing second controlling outputs; pattern counter means connected to the second means, with the second controlling outputs controlling the clocking rate of the pattern counter means so that said pattern counter means provides pulse pattern data; third memory means connected to the pattern counter means for storing the pulse pattern data therefrom; and means connected to the third memory means for accessing the stored pulse pattern data.

Claim 18

A pulse generator as described by claim 14, wherein the first means includes: first logic means connected to an external signal source for receiving clock and trigger pulses therefrom and for providing a clock output in response thereto; second logic means connected to an external command source for receiving commands therefrom, and connected to the first logic means for applying said commands thereto so that the first logic means provides the clock output; and multifunction counter means connected to the first logic means and responsive to the clock output therefrom for providing the first controlling outputs.