Method and apparatus for arranging access of vram to provide accelerated writing of vertical lines to an output display

Claim 2

In a graphics display system having a frame buffer for storing a plurality of pixels each having an associated X address and Y address, said frame buffer arranged in a plurality of VRAM banks, each VRAM bank having a control input and data input, said frame buffer having a multiplexor and a pixel counter for sequencing data from said VRAM banks for display, a VRAM access circuit comprising: means for selectively mapping pixel data to said VRAM banks under control of a first select; means for selectively mapping a plurality of control signals to said control inputs of said VRAM banks under control of a second select; counter means for generating a plurality of line signals indicating a line number for an output pixel as said output pixel is sequenced from said frame buffer; and logic means coupled to receive said line signals and to receive a plurality of pixel number signals from said pixel counter, said logic means generating a plurality of multiplexor select signals, said multiplexor select signals coupled to said multiplexor for sequencing said pixel data for display; whereby said pixel data is selectively mapped to said VRAM banks.

Claim 3

The circuit defined by claim 1, wherein said first select and said second select are coupled to lower order bits of said Y address of said pixels.

Claim 4

In a graphics display system having a frame buffer for storing a plurality of pixels each having an associated X address and Y address, said frame buffer arranged as four VRAM banks, said frame buffer having a multiplexor and a pixel counter for sequencing data from said VRAM banks for display, a VRAM access circuit comprising: first swapping means coupled to receive pixel data for four adjacent pixels and transfer said pixel data to said VRAM banks, said pixel data received on a first input and a second input and a third input and a fourth input which map to a first output and a second output and a third output and a fourth output according to the state of a pair of first select signals, said first output coupled to a data input of a first VRAM bank, said second output coupled to a data input of a second VRAM bank, said third output coupled to a data input of a third VRAM bank, said fourth output coupled to a data input of a fourth VRAM bank; second swapping means coupled to receive four control signals and transfer said control signals to control inputs of said VRAM banks, said control signals received on a fifth input and a sixth input and a seventh input and an eighth input which map to a fifth output and a sixth output and a seventh output and an eighth output according to the state of a pair of second select signals, said fifth output coupled to a control input of said first VRAM bank, said sixth output coupled to a control input of said second VRAM bank, said seventh output coupled to a control input of said third VRAM bank, said eighth output coupled to a control input of said fourth VRAM bank; counter means for generating a pair of line signals indicating a line number for an output pixel as said output pixel is sequenced from said frame buffer; and logic means coupled to receive said line signals and receive a pair of pixel number signals from said pixel counter, said logic means generating a pair of multiplexor select signals from said multiplexor; whereby said pixel data for said four adjacent pixels is selectively mapped to said four VRAM banks.

Claim 5

In a graphics display system having a frame buffer for storing a plurality of pixels each having an associated X address and Y address, said frame buffer arranged as four VRAM banks, said frame buffer having a multiplexor and a pixel counter for sequencing data from said VRAM banks for display, a VRAM access circuit comprising: first swapping means coupled to receive pixel data for four adjacent pixels and transfer said pixel data to said VRAM banks, said pixel data received on a first input and a second input and a third input and a fourth input which map to a first output and a second output and a third output and a fourth output according to the state of a pair of first select signals, said first output coupled to a data input of a first VRAM bank, said second output coupled to a data input of a second VRAM bank, said third output coupled to a data input of a third VRAM bank, said fourth output coupled to a data input of a fourth VRAM bank; second swapping means coupled to receive four control signals and transfer said control signals to control inputs of said VRAM banks, said control signals received on a fifth input and a sixth input and a seventh input and an eighth input which map to a fifth output and a sixth output and a seventh output and an eighth output according to the state of a pair of second select signals, said fifth output coupled to a control input of said first VRAM bank, said sixth output coupled to a control input of said second VRAM bank, said seventh output coupled to a control input of said third VRAM bank, said eighth output coupled to a control input of said fourth VRAM bank; counter means for generating a pair of line signals indicating a line number for an output pixel as said output pixel is sequenced from said frame buffer; and logic means coupled to receive said line signals and receive a pair of pixel number signals from said pixel counter, said logic means generating a pair of multiplexor select signals from said multiplexor; whereby said pixel data for said four adjacent pixels is selectively mapped to said four VRAM banks.

Claim 6

The circuit defined by claim 3, wherein said first select signals comprise and S0 signal and an S1 signal such that if said S0 and S1 are both in a first state then said first input is mapped to said first output and said second input is mapped to said second output and said third input is mapped to said third output and said fourth input is mapped to said fourth output.

Claim 7

The circuit defined by claim 3, wherein said first select signals comprise an S0 signal and an S1 signal such that if said S0 is in a first state and said S1 is in a second state then said first input is mapped to said third output and said second input is mapped to said fourth output and said third input is mapped to said first output and said fourth input is mapped to said second output.

Claim 8

The circuit defined by claim 3, wherein said first select signals comprise an S0 signal and an S1 signal such that if said S0 is in a second state and said S1 is in a first state then said first input is mapped to said second output and said second input is mapped to said first output and said third input is mapped to said fourth output and said fourth input is mapped to said third output.

Claim 9

The circuit defined by claim 3, wherein said first select signals comprise an S0 signal and an S1 signal such that if said S0 and S1 are both in a second state then said first input is mapped to said fourth output and said second input is mapped to said third output and said third input is mapped to said second output and said fourth input is mapped to said first output.

Claim 10

The circuit defined by claim 3, wherein said second select signals comprise an S0 signal and an S1 signal such that if said S0 and S1 are both in a first state then said fifth input is mapped to said fifth output and said sixth input is mapped to said sixth output and said seventh input is mapped to said seventh output and said eighth input is mapped to said eighth output.

Claim 11

The circuit defined by claim 3, wherein said second select signals comprise an S0 signal and an S1 signal such that if said S0 is in a first state and said S1 is in a second state then said fifth input is mapped to said seventh output and said sixth input is mapped to said eighth output and said seventh input is mapped to said fifth output and said eighth input is mapped to said sixth output.

Claim 12

The circuit defined by claim 3, wherein said second select signals comprise an S0 signal and an S1 signal such that if said S0 is in a second state and said S1 is in a first state then said fifth input is mapped to said sixth output and said sixth input is mapped to said fifth output and said seventh input is mapped to said eighth output and said eighth input is mapped to said seventh output.

Claim 13

The circuit defined by claim 3, wherein said second select signals comprise an S0 signal and an S1 signal such that if said S0 and S1 are both in a second state then said fifth input is mapped to said eighth output and said sixth input is mapped to said seventh output and said seventh input is mapped to said sixth output and said eighth input is mapped to said fifth output.

Claim 14

The circuit defined by claim 3, wherein said first select signals comprise an S0 signal and an S1 signal, said S1 signal coupled to a least significant bit of said Y address, said S0 signal coupled to a next to least significant bit of said Y address.

Claim 15

The circuit defined by claim 3, wherein said second select signals comprise an S0 signal and an S1 signal, said S1 signal coupled to a least significant bit of said Y address, said S0 signal coupled to a next to least significant bit of said Y address.

Claim 16

In a graphics display system having a frame buffer for storing a plurality of pixel each having an associated X address and Y address, said frame buffer arranged as four VRAM banks, a method for accessing VRAM comprising the steps of: receiving pixels data for four adjacent pixels, said pixel data comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; selectively swapping said pixel data to a first VRAM bank, a second VRAM bank, a third VRAM bank, and a fourth VRAM bank, according to the state of a first select signal and a second select signal; receiving a first control signal, a second control signal, a third control signal, and a fourth control signal; selectively swapping said first control signal, said second control signal, said third control signal, and said fourth control signal to a control input for said first VRAM bank, a control input for said second VRAM bank, a control input for said third VRAM bank, and a control input for said fourth VRAM bank, according to the state of said first select signal and said second select signal; generating a pair of line signals indicating a line number for an output pixel as said output pixel is sequenced from said frame buffer; and generating a pair of pixel number signals; reading said pixel data from said first VRAM bank, said second VRAM bank, said third VRAM bank, and said fourth VRAM bank, according to the state of said line signals and said pixel number signals; whereby said pixel data for said four adjacent pixels is selectively mapped to said four VRAM banks.

Claim 17

In a graphics display system having a frame buffer for storing a plurality of pixel each having an associated X address and Y address, said frame buffer arranged as four VRAM banks, a method for accessing VRAM comprising the steps of: receiving pixels data for four adjacent pixels, said pixel data comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; selectively swapping said pixel data to a first VRAM bank, a second VRAM bank, a third VRAM bank, and a fourth VRAM bank, according to the state of a first select signal and a second select signal; receiving a first control signal, a second control signal, a third control signal, and a fourth control signal; selectively swapping said first control signal, said second control signal, said third control signal, and said fourth control signal to a control input for said first VRAM bank, a control input for said second VRAM bank, a control input for said third VRAM bank, and a control input for said fourth VRAM bank, according to the state of said first select signal and said second select signal; generating a pair of line signals indicating a line number for an output pixel as said output pixel is sequenced from said frame buffer; and generating a pair of pixel number signals; reading said pixel data from said first VRAM bank, said second VRAM bank, said third VRAM bank, and said fourth VRAM bank, according to the state of said line signals and said pixel number signals; whereby said pixel data for said four adjacent pixels is selectively mapped to said four VRAM banks.

Claim 18

The method of claim 14, wherein the step of selectively swapping said pixel data comprises the steps of: if said first and second select signals are both in a first state, then mapping said first pixel to said first VRAM bank, said second pixel to said second VRAM bank, said third pixel to said third VRAM bank, and said fourth pixel to said fourth VRAM bank; if said first select signal is in said first state and said second select signal is in a second state, then mapping said first pixel to said third VRAM bank, said second pixel to said fourth VRAM bank, said third pixel to said first VRAM bank, and said fourth pixel to said second VRAM bank; if said first select signal is in said second state and said second select signal is in said first state, then mapping said first pixel to said second VRAM bank, said second pixel to said first VRAM bank, said third pixel to said fourth VRAM bank, and said fourth pixel to said third VRAM bank; if said first and second select signals are both in said second state, then mapping said first pixel to said fourth VRAM bank, said second pixel to said third VRAM bank, said third pixel to said second VRAM bank, and said fourth pixel to said first VRAM bank.

Claim 19

The method of claim 15, wherein said first select signal is coupled to a least significant bit of said Y address, and said second select signal is coupled to a next to least significant bit of said Y address.

Claim 20

The method of claim 14, wherein the step of selectively swapping said first control signal, said second control signal, said third control signal, and said fourth control signal comprises the steps of: if said first and second select signals are both in a first state, then mapping said first control signal to said control input for said first VRAM bank, said second control signal to said control input for said second VRAM bank, said third control signal to said control input for said third VRAM bank, and said fourth control signal to said control input for said fourth VRAM bank; it said first select signal is in said first state and said second select signal is in a second state, then mapping said first control signal to said control input for said third VRAM bank, said second control signal to said control input for said fourth VRAM bank, said third control signal to said control input for said first VRAM bank, and said fourth control signal to said control input for said second VRAM bank; if said first select signal is in said second state and said second select signal is in said first state, then mapping said first control signal to said control input for said second VRAM bank, said second control signal to said control input for said first VRAM bank, said third control signal to said control input for said fourth VRAM bank, and said fourth control signal to said control input for said third VRAM bank; if said first and second select signals are both in said second state, then mapping said first control signal to said control input for said fourth VRAM bank, said second control signal to said control input for said third VRAM bank, said third control signal to said control input for said second VRAM bank, and said fourth control signal to said control input for said first VRAM bank.

Claim 21

The method of claim 17, wherein said first select signal is coupled to a least significant bit of said Y address, and said second select signal is coupled to a next to least significant bit of said Y address.