Least-recently-used circuit

Claim 2

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a control signal to select said replaceable bank, each of said n means consisting of a single NAND gate having an output and an input; a first one of said n means for outputting a control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a control signal having said output of the kth one of said n means coupled to a kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; means, having an input coupled to an enable signal and to said outputs of said n means for outputting a control signal, and having an output, for detecting an absence of said control signal; and a transistor gate having a first, second and third terminal, said first terminal coupled to a reset terminal of said least-recently-used memory, said second terminal coupled to a means for activating said least-recently-used circuit and said third terminal coupled to said output of said means for detecting said absence of said control signal, for resetting each bit stored in said bit storage cells when said control signal is absent and whereby to select said replaceable bank is selected.

Claim 3

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a first control signal to select said replaceable bank, each of said n means consisting of a single NAND gate and having an output and an input; a first one of said n means for outputting a first control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a first control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a first control signal having said output of the kth one of said n means coupled to kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; means, having an output and an input coupled to an enable signal and to said outputs of said n means for outputting a first control signal, for detecting an absence of said first control signal; and means, consisting of a negated NOR gate having an input connected to said output of said means for detecting an absence of said first control signal and to an output of one and only one of said n means for outputting a first control signal, and having an output coupled to a given bank, for outputting a second control signal to select said given bank as said replaceable bank when said means for detecting outputs a signal indicating said absence of said first control signal.

Claim 4

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a first control signal to select said replaceable bank, each of said n means consisting of a single NAND gate and having an output and an input; a first one of said n means for outputting a first control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a first control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a first control signal having said output of the kth one of said n means coupled to kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; means, having an output and an input coupled to an enable signal and to said outputs of said n means for outputting a first control signal, for detecting an absence of said first control signal; and means, consisting of a negated NOR gate having an input connected to said output of said means for detecting an absence of said first control signal and to an output of one and only one of said n means for outputting a first control signal, and having an output coupled to a given bank, for outputting a second control signal to select said given bank as said replaceable bank when said means for detecting outputs a signal indicating said absence of said first control signal.

Claim 5

The least-recently-used circuit of claim 2 wherein said means for detecting an absence of said first control signal comprises a NAND gate.

Claim 6

The least-recently-used circuit of claim 2 wherein said negated NOR gate is constructed as an AND gate.

Claim 7

The least-recently-used circuit of claim 2 further comprising a means, coupled to said least-recently-used memory, for activating said least-recently-used circuit.

Claim 8

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a first control signal to select said replaceable bank, each of said n means having an output and an input; a first one of said n means for outputting a first control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a first control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a first control signal having said output of the kth one of said n means coupled to a kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; a register, which stores a given fixed second control signal, wherein said second control signal is independent of a previously asserted first control signal for selecting a predetermined replaceable bank; means, having an output and having an input coupled to said outputs of said n means for outputting a first control signal, for detecting an absence of said first control signal; and a multiplexer, having an output coupled to said n banks and having an input coupled to said outputs of said n means for outputting a first control signal, to said register and to said output of said means for detecting, which outputs said first control signal when said output of said means for detecting is asserted and said multiplexer outputs said second control signal when said output of said means for detecting is deasserted.

Claim 9

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a first control signal to select said replaceable bank, each of said n means having an output and an input; a first one of said n means for outputting a first control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a first control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a first control signal having said output of the kth one of said n means coupled to a kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; a register, which stores a given fixed second control signal, wherein said second control signal is independent of a previously asserted first control signal for selecting a predetermined replaceable bank; means, having an output and having an input coupled to said outputs of said n means for outputting a first control signal, for detecting an absence of said first control signal; and a multiplexer, having an output coupled to said n banks and having an input coupled to said outputs of said n means for outputting a first control signal, to said register and to said output of said means for detecting, which outputs said first control signal when said output of said means for detecting is asserted and said multiplexer outputs said second control signal when said output of said means for detecting is deasserted.

Claim 10

The least-recently-used circuit of claim 6 wherein each of said n means for outputting a first control signal comprises a NAND gate.

Claim 11

The least-recently-used circuit of claim 6 wherein said means for detecting an absence of said first control signal comprises a NAND gate.

Claim 12

The least-recently-used circuit of claim 6 further comprising a means, coupled to said least-recently-used memory, for activating said least-recently-used circuit.

Claim 13

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a control signal to select said replaceable bank, each of said n means having an output and an input; a first one of said n means for outputting a control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a control signal having said output of the kth one of said n means coupled to a kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; a gate, having an output coupled to said least-recently-used memory, an input and a gate enable; means, having an input coupled to an enable signal and to said outputs of said n means for outputting a control signal, and having an output coupled to said gate enable, for detecting an absence of said control signal and for enabling said gate when said absence is detected; and a register, coupled to said input of said gate memory, which outputs a fixed predetermined bit pattern to said bit storage cells of said least-recently-used memory to enable selection of a predetermined replaceable bank when said gate is enabled.

Claim 14

A least-recently-used circuit for selecting a replaceable bank in a memory having n banks comprising: a least-recently-used memory having a series of bit storage cells, wherein each cell represents a relative order of priority as between two banks in said memory in accordance with a value of a bit stored within said each cell and wherein each cell has a Q and a not-Q output; a set of n means for outputting a control signal to select said replaceable bank, each of said n means having an output and an input; a first one of said n means for outputting a control signal having said output of the first one of said n means coupled to a first bank and said input of the first one of said n means coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said first bank and remaining banks; an nth one of said n means for outputting a control signal having said output of the nth one of said n means coupled to an nth bank and said input of the nth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said nth bank and said first bank through n-1 banks; a kth one of said n means for outputting a control signal having said output of the kth one of said n means coupled to a kth bank and a first terminal of said input of the kth one of said n means coupled to said Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and first through k-1 banks and a second terminal of said input coupled to said not-Q output of select ones of said bit storage cells which represent a relative order of priority as between said kth bank and k+1 through nth banks, for 2≦k≦n-1; a gate, having an output coupled to said least-recently-used memory, an input and a gate enable; means, having an input coupled to an enable signal and to said outputs of said n means for outputting a control signal, and having an output coupled to said gate enable, for detecting an absence of said control signal and for enabling said gate when said absence is detected; and a register, coupled to said input of said gate memory, which outputs a fixed predetermined bit pattern to said bit storage cells of said least-recently-used memory to enable selection of a predetermined replaceable bank when said gate is enabled.

Claim 15

The least-recently-used circuit of claim 10 wherein each of said n means for outputting a control signal comprises a NAND gate.

Claim 16

The least-recently-used circuit of claim 10 wherein said means for detecting an absence of said control signal comprises a NAND gate.

Claim 17

The least-recently-used circuit of claim 10 further comprising a means, coupled to said least-recently-used memory, for activating said least-recently-used circuit.