Semiconductor device in which gate region is precisely aligned with source and drain regions

Claim 2

A transistor device comprising a semiconductor substrate having a source region and a drain region, said source and drain regions of said substrate being separated from each other by a gate region of said substrate; said gate region being substantially homogeneous with all other portions of said semiconductor substrate outside said source and drain regions; said source and drain regions being doped differently from said gate region; a surface of said semiconductor substrate being substantially isoplanar over said source, drain and gate regions; an abrupt transition occurring within said semiconductor substrate between said source region and said gate region, and an abrupt transition occurring within said semiconductor substrate between said drain region and said gate region; said device further comprising a metal gate of substantially uniform thickness; a first boundary of said metal gate being precisely aligned generally collinearly with a boundary of said source region of said substrate at said abrupt transition between said source region and said gate region, a second boundary of said metal gate being precisely aligned generally collinearly with a boundary of said drain region of said substrate at said abrupt transition between said drain region and said gate region; said first and second boundaries of said metal gate being generally perpendicular to said substantially isoplanar surface of said semiconductor substrate; the precise alignment of said first boundary of said metal gate with said boundary of said source region at said abrupt transition between said source region and said gate region, and the precise alignment of said second boundary of said metal gate with said boundary of said drain region at said abrupt transition between said drain region and said gate region, substantially precluding any significant overlap of said metal gate with edge portions of said source and drain regions adjacent said abrupt transitions between said gate region and said source and drain regions; said device also comprising a layer of substantially homogeneous dielectric material of substantially uniform thickness formed on said surface of said semiconductor substrate over said source region and said drain region, said layer of substantially homogeneous dielectric material substantially covering all of said source and drain regions; said layer of dielectric material having a first edge portion that abuts said first boundary of said metal gate, said first edge portion of said layer of dielectric material being precisely aligned with said boundary of said source region at said abrupt transition between said source region and said gate region; said layer of dielectric material having a second edge portion that abuts said second boundary of said metal gate, said second edge portion of said layer of dielectric material being precisely aligned with said boundary of said drain region at said abrupt transition between said drain region and said gate region; said first and second edge portions of said layer of dielectric material being generally perpendicular to said substantially isoplanar surface of said semiconductor substrate so as to define side walls of a channel of substantially uniform width over said gate region of said substrate, said metal gate being formed within said channel between said side walls of said channel; the thickness of said layer of dielectric material on said isoplanar surface of said substrate over said source and drain regions being sufficient so that said metal gate within said channel is shadowed by said first and second edge portions of said layer of dielectric material from light incident upon said layer of dielectric material at an oblique angle of incidence.

Claim 3

The device of claim 1 wherein said semiconductor material consists substantially of silicon, and wherein said layer of dielectric material on said surface of said substrate over said source and drain regions consists substantially of silicon dioxide.

Claim 4

A junction field effect transistor (JFET) device comprising a semiconductor substrate having a source region and a drain region, said source and drain regions of said substrate being separated from each other by a gate region of said substrate; said gate region being substantially homogeneous with all other portions of said semiconductor substrate outside said source and drain regions; said source and drain regions being doped differently from said gate region; a surface of said substrate being substantially isoplanar over said source, drain and gate regions; an abrupt transition occurring within said substrate between said source region and said gate region, and an abrupt transition occurring within said substrate between said drain region and said gate region; said device further comprising a metal gate of substantially uniform thickness formed directly on a portion of said isoplanar surface of said semiconductor substrate over said gate region between said source region and said drain region; a first boundary of said metal gate being precisely aligned generally collinearly with a boundary of said source region of said substrate at said abrupt transition between said source region and said gate region, a second boundary of said metal gate being precisely aligned generally collinearly with a boundary of said drain region of said substrate at said abrupt transition between said drain region and said gate region; said first and second boundaries of said metal gate being generally perpendicular to said substantially isoplanar surface of said substrate; the precise alignment of said first boundary of said metal gate with said boundary of said source region at said abrupt transition between said source region and said gate region, and the precise alignment of said second boundary of said metal gate with said boundary of said drain region at said abrupt transition between said drain region and said gate region, substantially precluding any significant overlap of said metal gate with edge portions of said source and drain regions adjacent said abrupt transitions between said gate region and said source and drain regions; said JFET device also comprising a layer of substantially homogeneous dielectric material of substantially uniform thickness on said surface of said semiconductor substrate over said source region and said drain region, said layer of substantially homogeneous dielectric material substantially covering all of said source and drain regions; said layer of dielectric material having a first edge portion that abuts said first boundary of said metal gate formed on said portion of said surface of said substrate over said gate region of said substrate, said first edge portion of said layer of dielectric material being precisely aligned with said boundary of said source region at said abrupt transition between said source region and said gate region; said layer of dielectric material having a second edge portion that abuts said second boundary of said metal gate formed on said portion of said surface of said substrate over said gate region of said substrate, said second edge portion of said layer of dielectric material being precisely aligned with said boundary of said source region at said abrupt transition between said drain region and said gate region; said first and second edge portions of said layer of dielectric material being generally perpendicular to said substantially isoplanar surface of said substrate so as to define side walls of a channel of substantially uniform width over said gate region of said substrate, said metal gate being formed within said channel between said side walls of said channel; the thickness of said layer of dielectric material on said isoplanar surface of said substrate over said source region and said drain region being sufficient so that said metal gate is shadowed by said first and second edge portions of said layer of dielectric material from light incident upon said layer of dielectric material at an oblique angle of incidence.

Claim 5

A junction field effect transistor (JFET) device comprising a semiconductor substrate having a source region and a drain region, said source and drain regions of said substrate being separated from each other by a gate region of said substrate; said gate region being substantially homogeneous with all other portions of said semiconductor substrate outside said source and drain regions; said source and drain regions being doped differently from said gate region; a surface of said substrate being substantially isoplanar over said source, drain and gate regions; an abrupt transition occurring within said substrate between said source region and said gate region, and an abrupt transition occurring within said substrate between said drain region and said gate region; said device further comprising a metal gate of substantially uniform thickness formed directly on a portion of said isoplanar surface of said semiconductor substrate over said gate region between said source region and said drain region; a first boundary of said metal gate being precisely aligned generally collinearly with a boundary of said source region of said substrate at said abrupt transition between said source region and said gate region, a second boundary of said metal gate being precisely aligned generally collinearly with a boundary of said drain region of said substrate at said abrupt transition between said drain region and said gate region; said first and second boundaries of said metal gate being generally perpendicular to said substantially isoplanar surface of said substrate; the precise alignment of said first boundary of said metal gate with said boundary of said source region at said abrupt transition between said source region and said gate region, and the precise alignment of said second boundary of said metal gate with said boundary of said drain region at said abrupt transition between said drain region and said gate region, substantially precluding any significant overlap of said metal gate with edge portions of said source and drain regions adjacent said abrupt transitions between said gate region and said source and drain regions; said JFET device also comprising a layer of substantially homogeneous dielectric material of substantially uniform thickness on said surface of said semiconductor substrate over said source region and said drain region, said layer of substantially homogeneous dielectric material substantially covering all of said source and drain regions; said layer of dielectric material having a first edge portion that abuts said first boundary of said metal gate formed on said portion of said surface of said substrate over said gate region of said substrate, said first edge portion of said layer of dielectric material being precisely aligned with said boundary of said source region at said abrupt transition between said source region and said gate region; said layer of dielectric material having a second edge portion that abuts said second boundary of said metal gate formed on said portion of said surface of said substrate over said gate region of said substrate, said second edge portion of said layer of dielectric material being precisely aligned with said boundary of said source region at said abrupt transition between said drain region and said gate region; said first and second edge portions of said layer of dielectric material being generally perpendicular to said substantially isoplanar surface of said substrate so as to define side walls of a channel of substantially uniform width over said gate region of said substrate, said metal gate being formed within said channel between said side walls of said channel; the thickness of said layer of dielectric material on said isoplanar surface of said substrate over said source region and said drain region being sufficient so that said metal gate is shadowed by said first and second edge portions of said layer of dielectric material from light incident upon said layer of dielectric material at an oblique angle of incidence.

Claim 6

The JFET device of claim 3 wherein the thickness of said layer of dielectric material on said surface of said substrate over said source and drain regions is at least equal to the width of said channel over said gate region.

Claim 7

The JFET device of claim 3 wherein said layer of dielectric material on said surface of said substrate over said source and drain regions consists substantially of an oxide.

Claim 8

The JFET device of claim 5 wherein said semiconductor material consists substantially of silicon, and wherein said layer of dielectric material on said surface of said substrate over said source and drain regions consists substantially of silicon dioxide.