Time-division multiplex transmission system

Claim 2

An asynchronous time-division multiplex transmission system, comprising a plurality of auxiliary lines, a trunk line, and an interconnection element for transmitting cells from resepctive auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; and said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises means for storing a first status in the respective control buffer when a cell is stored in the associated intersection buffer; the allocation circuit comprises means for storing, in the respective control buffers of the hierarchically lower allocation elements, a respective second status for each first status stored in a respective hierarchically higher allocation element, and the allocation circuit further comprises means for evaluating the associated control buffer of each allocation element in reverse hierarchical order and, responsive to said associated control buffers having a first status stored therein, releasing the associated intersection buffer for reading out a cell stored therein.

Claim 3

A system as claimed in claim 1, characterized in that each allocation element stores a binary "one" in the associated control buffer to define said first status; and stores a binary "zero" in said associated control buffer to define said second status.

Claim 4

A system as claimed in claim 1, characterized in that each allocation element except for the hierarchically lowest allocation element comprises means for generating an arrival signal after a first status has been stored in the associated control buffer, said arrival signal being passed from one allocation element to the next in a hierarchically decreasing order; and the means for storing said respective second status in the corresponding control buffer of each hierarchically lower allocation element stores such status after the arrival signal has been passed to said hierarchically lower allocation element.

Claim 5

An asynchronous time-division multiplex transmission system, comprising a plurality of auxiliary lines, a trunk line, and an interconnection element for transmitting cells from respective auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; and said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises means for storing a first status in the respective control buffer when a cell is stored in the associated intersection buffer; and the allocation circuit comprises: means for storing in the respective control buffers of the hierarchically lower allocation elements, a respective second status for each first status stored in a respective hierarchically higher allocation element, a cell request circuit for producing a release signal at the beginning of a time frame, the allocation element having the lowest hierarchical order being released by said release signal for evaluation of its associated control buffer and, responsive to said associated control buffer having a first status as the oldest status stored therein, releasing the associated intersection buffer for reading out a cell stored therein; and means for passing on said release signal from one allocation element to the next in hierarchically increasing order after the associated control buffer has been evaluated and a second status read out as the oldest status stored in the associated control buffer.

Claim 6

An asynchronous time-division multiplex transmission system, comprising a plurality of auxiliary lines, a trunk line, and an interconnection element for transmitting cells from respective auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; and said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises means for storing a first status in the respective control buffer when a cell is stored in the associated intersection buffer; and the allocation circuit comprises: means for storing in the respective control buffers of the hierarchically lower allocation elements, a respective second status for each first status stored in a respective hierarchically higher allocation element, a cell request circuit for producing a release signal at the beginning of a time frame, the allocation element having the lowest hierarchical order being released by said release signal for evaluation of its associated control buffer and, responsive to said associated control buffer having a first status as the oldest status stored therein, releasing the associated intersection buffer for reading out a cell stored therein; and means for passing on said release signal from one allocation element to the next in hierarchically increasing order after the associated control buffer has been evaluated and a second status read out as the oldest status stored in the associated control buffer.

Claim 7

A system as claimed in claim 4, characterized in that each allocation element stores a binary "one" in the associated control buffer to define said first status; and stores a binary "zero" in said associated control buffer to define said second status.

Claim 8

A system as claimed in claim 4, characterized in that each allocation element except for the hierarchically lowest allocation element comprises means for generating an arrival signal after a first status has been stored in the associated control buffer, said arrival signal being passed from one allocation element to the next in a hierarchically decreasing order; and the means for storing said respective second status in the corresponding control buffer of said next allocation element stores such status after the arrival signal has been passed to said next allocation element.

Claim 9

A system as claimed in claim 6, characterized in that each allocation element stores a binary "one" in the associated control buffer to define said first status; and stores a binary "zero" in said associated control buffer to define said second status.

Claim 10

An asynchronous time-division multiplex transmission system, comprising a plurality of auxiliary lines, a trunk line, and an interconnection element for transmitting cells from respective auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; and said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises a write controller and a read controller, said write controller writing a first status into the respective control buffer of that allocation element when the associated cell filter signals that a cell destined for said trunk line has arrived, each allocation element except for the hierarchically lowest allocation element comprises means for generating an arrival signal after a first status has been stored in the associated control buffer, said arrival signal being passed from one allocation element to the next in a hierarchically decreasing order, each write controller writes a second status into the control buffer after the arrival signal arrives from the higher hierarchy allocation element, thereby storing a respective second status for each first status stored in a respective hierarchically higher allocation element, the allocation circuit further comprises a cell request circuit for producing a release signal at the beginning of a time frame, the allocation element having the lowest hierarchical order being released by said release signal for evaluation of its associated control buffer and, responsive to said associated control buffer having a first status as the oldest status stored therein, releasing the associated intersection buffer for reading out a cell stored therein; and means for passing on said release signal from one allocation element to the next in hierarchically increasing order after the associated control buffer has been evaluated and a second status read out as the oldest status stored in the associated control buffer, and each read controller is coupled to the respective control buffer for releasing the associated intersection buffer for read out responsive to receipt of a release signal from a lower hierarchical allocation element and read out of a first status as the oldest status stored in the respective control buffer of said each read controller.

Claim 11

An asynchronous time-division multiplex transmission system, comprising a plurality of auxiliary lines, a trunk line, and an interconnection element for transmitting cells from respective auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; and said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises a write controller and a read controller, said write controller writing a first status into the respective control buffer of that allocation element when the associated cell filter signals that a cell destined for said trunk line has arrived, each allocation element except for the hierarchically lowest allocation element comprises means for generating an arrival signal after a first status has been stored in the associated control buffer, said arrival signal being passed from one allocation element to the next in a hierarchically decreasing order, each write controller writes a second status into the control buffer after the arrival signal arrives from the higher hierarchy allocation element, thereby storing a respective second status for each first status stored in a respective hierarchically higher allocation element, the allocation circuit further comprises a cell request circuit for producing a release signal at the beginning of a time frame, the allocation element having the lowest hierarchical order being released by said release signal for evaluation of its associated control buffer and, responsive to said associated control buffer having a first status as the oldest status stored therein, releasing the associated intersection buffer for reading out a cell stored therein; and means for passing on said release signal from one allocation element to the next in hierarchically increasing order after the associated control buffer has been evaluated and a second status read out as the oldest status stored in the associated control buffer, and each read controller is coupled to the respective control buffer for releasing the associated intersection buffer for read out responsive to receipt of a release signal from a lower hierarchical allocation element and read out of a first status as the oldest status stored in the respective control buffer of said each read controller.

Claim 12

A system as claimed in claim 8, characterized in that each allocation element stores a binary "one" in the associated control buffer to define said first status; and stores a binary "zero" in said associated control buffer to define said second status.

Claim 13

A system as claimed in claim 8, characterized in that, except for the write controller of the allocation element having the lowest hierarchical order, said means for generating an arrival signal when a cell is stored in the associated intersection buffer comprises the respective write controller; and that after generating a respective arrival signal responsive to storage of a respective cell in the respective associated intersection buffer, the write controllers of the hierarchically lower allocation elements pass on the arrival signal in hierarchically decreasing order.

Claim 14

A system as claimed in claim 10, characterized in that, except for the read controller of the hierarchically highest allocation element, after receipt of a release signal, each read controller passes the release signal in a hierarchically increasing order responsive to reading out a second status signal from said buffer.

Claim 15

A system as claimed in claim 10, characterized in that each allocation element stores a binary "one" in the associated control buffer to define said first status; and stores a binary "zero" in said associated control buffer to define said second status.

Claim 16

An interconnection element for use in an asynchronous time-division multiplex transmission system which comprises a plurality of auxiliary lines, and a trunk line, said element transmitting cells from respective auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises means for storing a first status in the respective control buffer when a cell is stored in the associated intersection buffer; the allocation circuit comprises means for storing, in the respective control buffers of the hierarchically lower allocation elements, a respective second status for each first status stored in a respective hierarchically higher allocation element, and the allocation circuit further comprises means for evaluating the associated control buffer of each allocation element in reverse hierarchical order and, responsive to said associated control buffer having a first status read out therefrom, releasing the associated intersection buffer for reading out a cell stored therein.

Claim 17

An interconnection element for use in an asynchronous time-division multiplex transmission system which comprises a plurality of auxiliary lines, and a trunk line, said element transmitting cells from respective auxiliary lines and destined for said trunk line, where each cell contains path identification information, said element including a corresponding plurality of cell filters each coupled to a respective auxiliary line; a corresponding plurality of intersection buffers each coupled to a respective cell filter; and an allocation circuit; each cell filter comprising means for determining if the path identification, contained in a cell received on the auxiliary line coupled thereto, is allocated to said trunk line, and then passing a cell so allocated to be stored in the corresponding intersection buffer; said allocation circuit controlling reading out of the cells from the intersection buffers onto the trunk line, characterized in that the allocation circuit comprises a chain of hierarchically structured allocation elements, each allocation element being associated with a respective intersection buffer and comprising a respective control buffer, each allocation element comprises means for storing a first status in the respective control buffer when a cell is stored in the associated intersection buffer; the allocation circuit comprises means for storing, in the respective control buffers of the hierarchically lower allocation elements, a respective second status for each first status stored in a respective hierarchically higher allocation element, and the allocation circuit further comprises means for evaluating the associated control buffer of each allocation element in reverse hierarchical order and, responsive to said associated control buffer having a first status read out therefrom, releasing the associated intersection buffer for reading out a cell stored therein.

Claim 18

An interconnection element as claimed in claim 13, characterized in that each allocation element stores a binary "one" in the associated control buffer to define said first status; and stores a binary "zero" in said associated control buffer to define said second status.

Claim 19

An interconnection element as claimed in claim 13, characterized in that each allocation element except for the hierarchically lowest allocation element comprises means for generating an arrival signal after a first status has been stored in the associated control buffer, said arrival signal being passed from one allocation element to the next in a hierarchically decreasing order; and the means for storing said second status in the corresponding control buffer of a hierarchically lower allocation element stores such status after the arrival signal has been passed to said hierarchically lower allocation element.

Claim 20

An element as claimed in claim 13, characterized in that said means for evaluating comprises: a cell request circuit for producing a release signal at the beginning of a time frame, the allocation element having the lowest hierarchical order being released by said release signal for evaluation of its associated control buffer and, responsive to said associated control buffer having a first status stored therein, releasing the associated intersection buffer for reading out a cell stored therein; and means for passing on said release signal from one allocation element to the next in hierarchically increasing order after the associated control buffer has been evaluated and a second status read out from the associated control buffer.

Claim 21

An interconnection element as claimed in claim 16, characterized in that each allocation element except for the hierarchically lowest allocation element comprises means for generating an arrival signal after a first status has been stored in the associated control buffer, said arrival signal being passed from one allocation element to the next in a hierarchically decreasing order; and the means for storing said second status in the corresponding control buffer of a hierarchically lower allocation element stores such status after the arrival signal has been passed to said hierarchically lower allocation element.

Claim 22

An interconnection element as claimed in claim 17, characterized in that each allocation element comprises a write controller and a read controller, said write controller writing a first status into the associated control buffer when an associated cell filter signals that a cell destined for said trunk line has arrived, and subsequently writing the second status into the control buffer after an arrival signal arrives from the higher hierarchy allocation element; and said read controller being coupled to the respective control buffer for releasing the associated intersection buffer for read out responsive to receipt of a release signal from a lower hierarchical allocation element and readout of a first status in the respective control buffer.

Claim 23

An interconnection element as claimed in claim 18, characterized in that, except for the write controller of the allocation element having the lowest hierarchical order, said means for generating an arrival signal when a cell is stored in the associated intersection buffer comprises the respective write controller; and that after generating a respective arrival signal responsive to storing of a respective cell in the respective associated intersection buffer, the write controllers of the hierarchically lower allocation elements pass on the arrival signal in hierarchically decreasing order.

Claim 24

An interconnection element as claimed in claim 19, characterized in that, except for the read controller of the hierarchically highest allocation element, after receipt of a release signal, each read controller passes the release signal in a hierarchically increasing order responsive to reading out a second status signal from said buffer.