Patent US5138455A successfully refreshed from Google Patents.
US5138455A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video signal processing circuit for compressed picture insertion function of television receiver
Assignee: Panasonic Holdings Corp
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Filing: 1991-05-28
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Granted: 1992-08-11
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Expires: 2011-05-28
Abstract
Abstract A video signal processing circuit for providing a compressed picture insertion function in a television receiver, whereby a compressed-size picture expressed by one video signal is displayed as an insert within a full-size picture that is expressed by another video signal, by demodulating and combining the video signals, which can be of respectively different television standards, such as the PAL and MUSE standards. The circuit utilizes only one demodulator circuit for one video signal and two demodulator circuits for the other signal. When one of the video signals is in accordance with a broadcast standard such as the MUSE standard, which requires a large-scale demodulator circuit, a significant reduction in overall circuit scale is achieved by comparsion with the prior art, in which two demodulator circuits are required for each of the video signals.
Inventors
- 👤 Naoji Okumura
- 👤 Hirohiko Sakashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:00
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/445; H04N5/45
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
278 words
A video signal processing circuit comprising: a first analog-to-digital converter coupled to convert a first analog video signal to a digital video signal; first and second demodulator circuits having respective output terminals connected in common and each coupled to receive said digital video signal from said first analog-to-digital converter; a second analog-to-digital converter coupled to receive a second analog video signal, for converting said second analog video signal to a digital video signal; a third demodulator circuit for demodulating said digital video signal produced from said second analog-to-digital converter; a first switching circuit for selecting one of said output signal produced from said common output terminal of said first and second demodulator circuits and an output signal produced from said third demodulator circuit, to be outputted therefrom; a second switching circuit for selecting one of said output signal produced from said common output terminal of said first and second demodulator circuits and said output signal produced from said third demodulator circuit; a compression circuit for effecting time axis compression of an output signal produced from said second switching circuit, to produce a compressed output signal, and for producing a switching signal; a third switching circuit for inserting an said compressed output signal produced from said compression circuit into said output signal from said first switching circuit, in accordance with said switching signal which is produced from said compression circuit; a switching control circuit for controlling respective operations of said first and second switching circuits in accordance with a required mode of compressed-picture insertion; and a digital-to-analog converter for converting an output signal produced from said third switching circuit from a digital video signal to an analog video signal.
Claim 2
Dependent Claim
278 words
A video signal processing circuit comprising: a first analog-to-digital converter coupled to convert a first analog video signal to a digital video signal; first and second demodulator circuits having respective output terminals connected in common and each coupled to receive said digital video signal from said first analog-to-digital converter; a second analog-to-digital converter coupled to receive a second analog video signal, for converting said second analog video signal to a digital video signal; a third demodulator circuit for demodulating said digital video signal produced from said second analog-to-digital converter; a first switching circuit for selecting one of said output signal produced from said common output terminal of said first and second demodulator circuits and an output signal produced from said third demodulator circuit, to be outputted therefrom; a second switching circuit for selecting one of said output signal produced from said common output terminal of said first and second demodulator circuits and said output signal produced from said third demodulator circuit; a compression circuit for effecting time axis compression of an output signal produced from said second switching circuit, to produce a compressed output signal, and for producing a switching signal; a third switching circuit for inserting an said compressed output signal produced from said compression circuit into said output signal from said first switching circuit, in accordance with said switching signal which is produced from said compression circuit; a switching control circuit for controlling respective operations of said first and second switching circuits in accordance with a required mode of compressed-picture insertion; and a digital-to-analog converter for converting an output signal produced from said third switching circuit from a digital video signal to an analog video signal.
Claim 3
Dependent Claim
39 words
A video signal processing circuit according to claim 1, wherein said first demodulator circuit is adapted for demodulating a high-definition television signal, and each of said second and third demodulator circuits is adapted for demodulating a conventional television signal.
Claim 4
Dependent Claim
322 words
A signal processing circuit comprising: a first analog-to-digital converter for converting a first analog video signal to a digital signal; a first demodulator circuit for demodulating said digital signal from said first analog-to-digital converter; a second analog-to-digital converter for converting a second analog video signal to a digital signal; a first switching circuit for selecting one of an output signal from said first analog-to-digital converter and an output signal from said second analog-to-digital converter; a second demodulator circuit for demodulating an output signal produced from said first switching circuit; a third demodulator circuit for demodulating said output signal from said second analog-to-digital converter; a second switching circuit coupled to receive an output signal produced from said second demodulator circuit, and having first and second output terminals, for selectively transferring said output signal produced from said second demodulator circuit to said first and second output terminals; a compression circuit having an input terminal coupled to said second output terminal of said second switching circuit and to an output terminal of said third demodulator circuit, for effecting time axis compression of an output signal produced from one of said second output terminal and said third demodulator circuit output terminal, and for producing a switching signal; a switching control circuit for controlling respective operations of said first and second switching circuits in accordance with a required mode of compressed-picture insertion; a third switching circuit having an input terminal coupled to said first output terminal of said second switching circuit and to an output terminal of said first demodulator circuit, for inserting an output signal produced from said compression circuit into said output signal produced from one of said second output terminal of said second switching circuit and said output terminal of said first demodulator circuit, in accordance with said switching signal; and a digital-to-analog converter for converting said output signal from said third switching circuit from a digital video signal to an analog video signal.
Claim 5
Dependent Claim
322 words
A signal processing circuit comprising: a first analog-to-digital converter for converting a first analog video signal to a digital signal; a first demodulator circuit for demodulating said digital signal from said first analog-to-digital converter; a second analog-to-digital converter for converting a second analog video signal to a digital signal; a first switching circuit for selecting one of an output signal from said first analog-to-digital converter and an output signal from said second analog-to-digital converter; a second demodulator circuit for demodulating an output signal produced from said first switching circuit; a third demodulator circuit for demodulating said output signal from said second analog-to-digital converter; a second switching circuit coupled to receive an output signal produced from said second demodulator circuit, and having first and second output terminals, for selectively transferring said output signal produced from said second demodulator circuit to said first and second output terminals; a compression circuit having an input terminal coupled to said second output terminal of said second switching circuit and to an output terminal of said third demodulator circuit, for effecting time axis compression of an output signal produced from one of said second output terminal and said third demodulator circuit output terminal, and for producing a switching signal; a switching control circuit for controlling respective operations of said first and second switching circuits in accordance with a required mode of compressed-picture insertion; a third switching circuit having an input terminal coupled to said first output terminal of said second switching circuit and to an output terminal of said first demodulator circuit, for inserting an output signal produced from said compression circuit into said output signal produced from one of said second output terminal of said second switching circuit and said output terminal of said first demodulator circuit, in accordance with said switching signal; and a digital-to-analog converter for converting said output signal from said third switching circuit from a digital video signal to an analog video signal.
Claim 6
Dependent Claim
39 words
A video signal processing circuit according to claim 3, wherein each of said first and third demodulator circuits is adapted for demodulating a conventional television signal, and said second demodulator circuit is adapted for demodulating a high-definition television signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |