Anodized polysilicon layer lower capacitor plate of a dram to increase capacitance

Claim 2

A storage capacitor, said capacitor having: a) an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer having a textured upper surface, said first doped silicon layer forming a storage node capacitor plate, wherein said textured upper surface is fabricated by anodizing said first doped silicon layer, said anodizing consuming portions of said first doped silicon layer to produce microstructures resembling elongated depressions, a porosity of said textured upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experienced during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate, and wherein said textured upper surface is further fabricated by texturizing the surface of said microstructures to further increase the surface area of said storage node capacitor plate, said texturizing producing three-dimensional asperities, said textured upper surface thereby defined by microstructures having three dimensional asperities; b) a dielectric layer having lower and upper surfaces, the textured upper surface of said first doped silicon layer being in contact at substantially all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the textured upper surface of said first doped silicon layer; and c) a further intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.

Claim 3

The storage capacitor of claim 1, wherein said first and second doped silicon layers are positively doped layers.

Claim 4

The storage capacitor of claim 2, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium, said trivalent atom effecting said positively doped layers.

Claim 5

The storage capacitor of claim 1, wherein said first and second doped silicon layers are negatively doped layers.

Claim 6

The storage capacitor of claim 4, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorous, said pentavalent atom effecting said negatively doped layers.

Claim 7

The storage capacitor of claim 1, wherein said first and second doped silicon layers are oppositely doped, one of said doped layers being negatively doped and one of said doped layers being positively doped.

Claim 8

The storage capacitor of claim 6, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium, said trivalent atom effecting said positively doped layers.

Claim 9

The storage capacitor of claim 6, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorous, said pentavalent atom effecting said negatively doped layers.

Claim 10

The storage capacitor of claim 1, wherein said dielectric layer further comprises silicon nitride.

Claim 11

The storage capacitor of claim 9, wherein the thickness of said silicon nitride layer is less than 100 Angstroms.

Claim 12

The storage capacitor of claim 1, wherein said anodizing further comprises submerging said first doped silicon layer in a container of electrolytic solution comprising hydrofluoric acid and subjecting said first doped silicon layer and said electrolytic solution to an electrolytic current, said current generated between two electrodes, one being an anode and one being a cathode.

Claim 13

The storage capacitor of claim 11, wherein said anode further comprises said first doped silicon layer.

Claim 14

The storage capacitor of claim 11, wherein said first doped silicon layer is a portion of a semiconductor wafer, said anode comprising said wafer.

Claim 15

The storage capacitor of claim 11, wherein said container is defined by walls, said cathode comprising said walls.

Claim 16

The storage capacitor of claim 11, wherein said cathode further comprises a platinum electrode immersed in said electrolytic solution parallel to said first doped silicon layer.

Claim 17

The storage capacitor of claim 11, further comprising said electrolytic current being within a range of 10 mA/cm 2 and 100 mA/cm 2 and with said hydrofluoric acid solution having a concentration between 10 to 60 percent by weight.

Claim 18

The storage capacitor of claim 16, wherein said porous film density falls within the range of 20 to 70 percent, with a preferred porous film density of substantially 45 percent.

Claim 19

The storage capacitor of claim 1, further comprising increasing said porous film density by the formation of an initial texturized surface on said first doped silicon layer prior to said anodizing and prior to said forming said textured upper surface.

Claim 20

The storage capacitor of claim 18, wherein a formation of an oxide layer on said first doped silicon layer prior to said anodizing forms said initial texturized surface, said oxide layer producing inhomogeneities to increase current flow and initiate depressions in said first doped silicon layer during said anodizing, said oxide layer subsequently removed to expose said initial texturized surface prior to said anodizing.

Claim 21

The storage capacitor of claim 19, wherein said oxide layer is grown with a wet oxidation.

Claim 22

The storage capacitor of claim 19, wherein said oxide layer is removed with a wet oxide etch.

Claim 23

The storage capacitor of claim 1, wherein a formation of an oxide layer on said microstructures subsequent to said anodizing forms said three-dimensional asperities on said microstructures, said oxide layer subsequently removed to expose the textured upper surface thus formed.

Claim 24

The storage capacitor of claim 22, wherein said oxide layer is grown with a wet oxidation.

Claim 25

The storage capacitor of claim 22, wherein said oxide layer is removed with a wet oxide etch.

Claim 26

The storage capacitor of claim 1, wherein said first and second doped silicon layers comprise polycrystalline silicon.

Claim 27

The storage capacitor of claim 1, wherein said first and second doped silicon layers comprise monocrystalline silicon.

Claim 28

An enhanced-capacitance DRAM cell comprising: a) a field-effect transistor (FET) constructed on a silicon substrate, a first portion of said substrate being conductively-doped to function as the FET's access node junction and a second portion of said substrate being conductively-doped to function as the FET's storage node junction; b) a storage capacitor, said capacitor having: 1) an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer having a textured upper surface, said first doped silicon layer forming a storage node capacitor plate in electrical communication with said storage node junction, wherein said textured upper surface is fabricated by anodizing said first doped silicon layer, said anodizing consuming portions of said first doped silicon layer to produce microstructures resembling elongated depressions, a porosity of said textured upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experienced during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate, and wherein said textured upper surface is further fabricated by texturizing the surface of said microstructures to further increase the surface area of said storage node capacitor plate, said texturizing producing three-dimensional asperities, said textured upper surface thereby defined by microstructures having three-dimensional asperities; 2) a dielectric layer having lower and upper surfaces, the textured upper surface of said first doped silicon layer being in contact at substantially all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the textured upper surface of said first doped silicon layer; and c) a further intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.

Claim 29

An enhanced-capacitance DRAM cell comprising: a) a field-effect transistor (FET) constructed on a silicon substrate, a first portion of said substrate being conductively-doped to function as the FET's access node junction and a second portion of said substrate being conductively-doped to function as the FET's storage node junction; b) a storage capacitor, said capacitor having: 1) an intrinsic silicon layer doped with an impurity to produce an extrinsic first doped silicon conductive layer having a textured upper surface, said first doped silicon layer forming a storage node capacitor plate in electrical communication with said storage node junction, wherein said textured upper surface is fabricated by anodizing said first doped silicon layer, said anodizing consuming portions of said first doped silicon layer to produce microstructures resembling elongated depressions, a porosity of said textured upper surface measured by a porous film density, said porous film density equal to the percent of weight loss for a given volume of said first doped silicon layer experienced during said anodizing, said anodizing increasing a surface area of said storage node capacitor plate, and wherein said textured upper surface is further fabricated by texturizing the surface of said microstructures to further increase the surface area of said storage node capacitor plate, said texturizing producing three-dimensional asperities, said textured upper surface thereby defined by microstructures having three-dimensional asperities; 2) a dielectric layer having lower and upper surfaces, the textured upper surface of said first doped silicon layer being in contact at substantially all points with the lower surface of said dielectric layer, said dielectric layer being substantially conformal with the textured upper surface of said first doped silicon layer; and c) a further intrinsic silicon layer doped with an impurity to produce an extrinsic second doped silicon conductive layer having lower and upper surfaces, said lower surface being in contact with the upper surface of said dielectric layer and being substantially conformal thereto.

Claim 30

The enhanced-capacitance DRAM cell of claim 27, further comprising said first and second doped silicon layers being positively doped, said first and second doped silicon layers being negatively doped, and said first and second doped silicon layers being oppositely doped, one of said doped layers being negatively doped and one of said doped layers being positively doped.

Claim 31

The enhanced-capacitance DRAM cell of claim 27, wherein said impurity is a trivalent atom comprising aluminum, boron and gallium.

Claim 32

The enhanced-capacitance DRAM cell of claim 28, wherein said impurity is a pentavalent atom comprising arsenic, antimony, and phosphorous.

Claim 33

The enhanced-capacitance DRAM cell of claim 27, wherein said dielectric layer further comprises silicon nitride.

Claim 34

The enhanced-capacitance DRAM cell of claim 31, wherein the thickness of said silicon nitride layer is less than 100 Angstroms.

Claim 35

The enhanced-capacitance DRAM cell of claim 27, wherein said anodizing further comprises submerging said first doped silicon layer in a container of electrolytic solution comprising hydrofluoric acid and subjecting said first doped silicon layer and said electrolytic solution to an electrolytic current, said current generated between two electrodes, one being an anode and one being a cathode.

Claim 36

The enhanced-capacitance DRAM cell of claim 33, wherein said anode comprises said first doped silicon layer and said silicon substrate.

Claim 37

The enhanced-capacitance DRAM cell of claim 33, wherein said container is defined by walls, said cathode comprising said walls and a platinum electrode immersed in said electrolytic solution parallel to said first doped silicon layer.

Claim 38

The enhanced-capacitance DRAM cell of claim 33, further comprising said electrolyte current being within a range of 10 mA/cm 2 and 100 mA/cm 2 and said hydrofluoric acid solution having a concentration between 10 to 60 percent by weight.

Claim 39

The enhanced-capacitance DRAM cell of claim 36, wherein said porous film density falls within the range of 20 to 70 percent, with a preferred porous film density of substantially 45 percent.

Claim 40

The enhanced-capacitance DRAM cell of claim 27, further comprising increasing said porous film density by the formation of an initial texturized surface on said first doped silicon layer prior to said anodizing and prior to said forming said textured upper surface.

Claim 41

The enhanced-capacitance DRAM cell of claim 38, wherein a formation of an oxide layer on said first doped silicon layer prior to said anodizing forms said initial texturized surface, said oxide layer producing inhomogeneities to increase current flow and initiate depressions in said first doped silicon layer during said anodizing, said oxide layer subsequently removed to expose said initial texturized surface prior to said anodizing.

Claim 42

The enhanced-capacitance DRAM cell of claim 27, wherein said first and second doped silicon layers comprise polycrystalline silicon and monocrystalline silicon.

Claim 43

The storage capacitor of claim 27, wherein a formation of an oxide layer on said microstructures subsequent to said anodizing forms said three-dimensional asperities on said microstructures, said oxide layer subsequently removed to expose the textured upper surface thus formed.