Communications arrangement for digital data processing system employing heterogeneous multiple processing nodes

Claim 2

A digital data processing system, comprising a plurality of nodes for performing processing tasks, one of said nodes being a host connected to every other node and having local access to a host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each memory structure being associated with one of said nodes, and for performing other processing tasks, each of said nodes, including said host, being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node, each of said nodes other than said host being arranged to insert said entry directly into said memory structure without assistance from said host, thereby leaving said host free to perform other processing tasks and communicate with other nodes, each of said nodes, including said host, being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer command contained in said entry.

Claim 3

A system as defined in claim 1 wherein said host initializes in said host memory a system descriptor blocking containing information from which said nodes can identify locations, in said host memory, of memory structures for storing entries, each node comprises a data register for storing a base address of said system descriptor block, and said host loads said base address of said system descriptor block into said data register of each node.

Claim 4

A system as defined in claim 1 wherein each node comprises a control register for storing at least one command from said host, and said host is arranged to load commands into said control registers of said nodes.

Claim 5

A system as defined in claim 3 wherein said at least one command comprises an initialization command to allow a node to begin transfers of information, a command to stop transfers of information, and a command to resume transfers of information.

Claim 6

A system as defined in claim 1 wherein, when an error occurs, a node notifies said host of said error, in order to obtain service from said host.

Claim 7

A system as defined in claim 5 wherein each node comprises an error register into which said node inserts an error code when an error occurs, said error code identifying said error, and each node comprises a status register into which said node inserts an indication of occurrence of an error in order to report said error to said host.

Claim 8

A system as defined in claim 1 wherein each node that retrieves an entry from a memory structure in said host memory with which said node is associated participates in a transfer of information with a node that initiated said transfer of information.

Claim 9

A system as defined in claim 7 wherein each of said nodes is arranged to initiate transfers of information both to and from said node, and said information transfer command indicates a direction of transfer.

Claim 10

A system as defined in claim 1 wherein said host initializes a queue buffer in said host memory, and said memory structures comprise queues located in said queue buffer.

Claim 11

A system as defined in claim 1 wherein each node comprises an attention register, and each node that inserts an entry an empty memory structure in said host memory associated with another node inserts a signal into an attention register of said another node to enable said another node to begin retrieving entries from said memory structure associated with said another node.

Claim 12

A system as defined in claim 10 wherein each node has an associated identification value, and said signal that said node inserts into said attention register comprises an identification value associated with said node.

Claim 13

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a host connected to each of said nodes and having local access to a host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each memory structure being associated with one of said nodes, and for performing other processing tasks, each of said nodes being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks, each of said nodes being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer command contained in said entry, wherein said host initializes a queue buffer in said host memory, and said memory structures comprise queues located in said queue buffer, said queue buffer comprises a queue buffer header comprising a plurality of queue headers each associated with a node, plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each node that inserts a new queue entry into a queue associated with another node utilizes a queue header associated with said another node in linking said new queue entry to said queue associated with said another node.

Claim 14

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a host connected to each of said nodes and having local access to a host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each memory structure being associated with one of said nodes, and for performing other processing tasks, each of said nodes being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks, each of said nodes being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer command contained in said entry, wherein said host initializes a queue buffer in said host memory, and said memory structures comprise queues located in said queue buffer, said queue buffer comprises a queue buffer header comprising a plurality of queue headers each associated with a node, plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each node that inserts a new queue entry into a queue associated with another node utilizes a queue header associated with said another node in linking said new queue entry to said queue associated with said another node.

Claim 15

A system as defined in claim 12 wherein said node that inserts said new queue entry into said queue associated with another node utilizes a node queue link field of said queue header associated with said another node and node queue link fields of a succession of queue entries located in said queue associated with said another node to locate a last queue entry in said queue associated with said another node, and links said new queue entry to said last queue entry.

Claim 16

A system as defined in claim 13 wherein said node that inserts said new queue entry into said queue associated with another node links said new queue entry to said last queue entry by loading a pointer to said new queue entry into a node queue link field of said last queue entry, and by loading a pointer to said queue header associated with said another node into a node queue link field of said new queue entry, to thereby link said new queue entry to said queue associated with said destination node.

Claim 17

A system as defined in claim 12 wherein said queue buffer header comprises a free queue header comprising a free queue link field to facilitate linking of queue entries into a free queue located in said queue buffer body, and said node that inserts said new queue entry into said queue associated with another node identifies said free queue header, utilizes said node queue link field of said free queue header to locate a free queue entry in said free queue, unlinks said free queue entry from said free queue, inserts said new queue entry into said free queue entry, and links said free queue entry into said queue associated with said another node.

Claim 18

A system as defined in claim 12 wherein said queue buffer header comprises a plurality of free queue headers each comprising a free queue link field to facilitate linking of queues entries into a respective plurality of free queues, said host initializes in said host memory a system descriptor block for identifying a free queue corresponding to each node, said node that inserts said new queue entry into said queue associated with another node utilizes said system descriptor bloc, to identify a free queue associated with said another node, identifies a free queue header associated with said another node, utilizes a node queue link field of said free queue header to locate a free queue entry in said free queue, unlinks said free queue entry from said free queue, inserts said new queue entry into said free queue entry, and links said free queue entry into said queue associated with said another node.

Claim 19

A system as defined in claim 16 wherein said system descriptor block comprises a plurality of node entries each associated with a node, each node entry identifying a free queue, and said node that inserts said new queue entry into said queue associated with another node locates a node entry in said system descriptor block associated with said another node, and locates a free queue identified by said node entry.

Claim 20

A system as defined in claim 17, wherein each node in said system descriptor block comprises a free queue descriptor comprising a free queue pointer to a free queue header in said queue buffer header, and said node that inserts said new queue entry into said queue associated with another node locates said free queue header identified by said free queue pointer, and determines whether a free queue associated with said free queue header comprise a free queue entry.

Claim 21

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a host connected to each of said nodes and having local access to a host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each memory structure being associated with one of said nodes, and for performing other processing tasks, each of said nodes being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks, each of said nodes being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer command contained in said entry, wherein said host initializes a queue buffer in said host memory, and said memory structures queues located in said queue buffer, said queue buffer comprises a queue buffer header comprising a plurality of queue headers each associated with a node, and a queue buffer body comprising a plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each of said nodes that retrieves an entry from a queue in said host memory with which said node is associated utilizes a queue header associated with said queue to retrieve said entry from said queue.

Claim 22

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a host connected to each of said nodes and having local access to a host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each memory structure being associated with one of said nodes, and for performing other processing tasks, each of said nodes being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks, each of said nodes being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer command contained in said entry, wherein said host initializes a queue buffer in said host memory, and said memory structures queues located in said queue buffer, said queue buffer comprises a queue buffer header comprising a plurality of queue headers each associated with a node, and a queue buffer body comprising a plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each of said nodes that retrieves an entry from a queue in said host memory with which said node is associated utilizes a queue header associated with said queue to retrieve said entry from said queue.

Claim 23

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a central memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, each of said nodes comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data directly between said nodal memory to which said processor has local access and another node by generating an entry identifying a data buffer in said nodal memory to which said processor has local access, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to particulate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access.

Claim 24

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a central memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, each of said nodes comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data directly between said nodal memory to which said processor has local access and another node by generating an entry identifying a data buffer in said nodal memory to which said processor has local access, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to particulate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access.

Claim 25

A system as defined in claim 20 wherein each node that retrieves an entry from a memory structure in said central memory with which said node is associated participates in a transfer of information with a data buffer located in a nodal memory of a node that initiated said transfer of information.

Claim 26

A system as defined in claim 21 wherein each of said nodes is arranged to initiate transfers of information both to and from a data buffer located in a nodal memory of said node, by inserting a said entry into a memory structure associated with another node, said entry indicating a direction of transfer.

Claim 27

A system as defined in claim 20 wherein said entry identifying said data buffer comprises a point identifying a location of said data buffer and a length filed that identifies a size of said data buffer.

Claim 28

A system as defined in claim 20 wherein said central memory comprises a queue buffer, and said memory structures comprise queue located in said queue buffer.

Claim 29

A system as defined in claim 20 wherein each node comprises an attention register, and each node that inserts an entry into an empty memory structure in said central memory associated with another node inserts a signal into an attention register of said another node to enable said another node to being retrieving entries from said memory structure associated with said another node.

Claim 30

A system as defined in claim 25 wherein each node has an associated identification value, and said signal that said node inserts into said attention register comprises an identification value associated with said node.

Claim 31

A system as defined in claim 20 wherein said central memory comprises a system descriptor block containing information for which said nodes can identify locations, in said central memory, of memory structures for storing entries, and each node comprises a data register for storing a base address of said system descriptor block.

Claim 32

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a central memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, each of said nodes comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data between said nodal memory and another node by generating an entry identifying a data buffer in said nodal memory, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to participate in a transfer of a block of data between said node and a data buffer identified in said entry, wherein said central memory comprises a queue buffer, said memory structures comprise queues located in said queue buffer, said queue buffer comprises a queue buffer header comprising a plurality of queue headers each associated with a node, and a queue buffer body comprising a plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each node that inserts a new queue entry into a queue associated with another node utilizes a queue header associated with said another node in linking said new queue entry to said queue associated with said another node.

Claim 33

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a central memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, each of said nodes comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data between said nodal memory and another node by generating an entry identifying a data buffer in said nodal memory, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to participate in a transfer of a block of data between said node and a data buffer identified in said entry, wherein said central memory comprises a queue buffer, said memory structures comprise queues located in said queue buffer, said queue buffer comprises a queue buffer header comprising a plurality of queue headers each associated with a node, and a queue buffer body comprising a plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each node that inserts a new queue entry into a queue associated with another node utilizes a queue header associated with said another node in linking said new queue entry to said queue associated with said another node.

Claim 34

A system as defined in claim 28 wherein said node that inserts said new queue entry into said queue associated with another node utilizes a node queue link field of said queue head associated with said another node and node queue link fields of a succession of queue entries located in said queue associated with said another node to locate a last queue entry in said queue associated with said another node, and links said new queue entry to said last queue entry.

Claim 35

A system as defined in claim 29 wherein said node that inserts said new queue entry into said queue associated with another node links said new queue entry to said last queue entry by loading a point to said new queue entry into a node queue link field of said last queue entry, and by loading a pointer to said queue header associated with said another node into a anode queue link field of said new queue entry, to thereby link said new queue entry to said queue associated with said destination node.

Claim 36

A system as defined in claim 28 wherein said queue buffer header comprises a free queue header comprising a free queue link field to facilitate linking of queue entries into a free queue located in said queue buffer body, and said node that inserts said new queue entry into said queue associated with another node identifies said free queue header, utilizes said node queue link field of said free queue header to locate a free queue entry in said free queue, unlinks said free queue entry from said free queue, inserts said new queue entry into said free queue entry, and links said free queue entry into said queue associated with said another node.

Claim 37

A system as defined in claim 28 wherein said queue buffer header comprises a plurality of free queue headers each comprising a free queue link field to facilitate linking of queue entries into a respective plurality of free queues, said central memory comprises a system descriptor block for identifying a free queue corresponding to each node, said node that inserts said new queue entry into said queue associated with another node utilizes said system descriptor block to identify a free queue associated with said another node, identifies a free queue header associated with said another node, utilizes a node queue link field of said free queue head to located a free queue entry in said free queue, unlinks said free queue entry from said free queue, inserts said new queue entry into said free queue entry, and links said free queue entry into said queue associated with said another node.

Claim 38

A system as described in claim 32 wherein said system descriptor block comprises a plurality of node entries each associated with a node, each node entry identifying a free queue, and said node that inserts said new queue entry into said queue associated with another node locates a node entry in said system descriptor block associated with said another node, and locates a free queue identified by said node entry.

Claim 39

A system as defined in claim 33, wherein each node entry in said system descriptor block comprises a free queue descriptor comprising a free queue pointer to a free queue header in said queue buffer header, and said node that inserts said new queue entry into said queue associated with another node locates said free queue header identified by said free queue pointer, and determines whether a free queue associated with said free queue header comprises a free queue entry.

Claim 40

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a central memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, each of said nodes comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data between said nodal memory and another node by generating an entry identifying a data buffer in said nodal memory, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to participate in a transfer of a block of data between said node and a data buffer identified in said entry, wherein said central memory comprises a queue buffer, said memory structures comprise queues located in said queue buffer, said queue buffer comprises a queue buffer header comprises a plurality of queue headers each associated with a node, and a queue buffer body comprising a plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each of said nodes that retrieves an entry from a queue in said central memory with which said node is associated utilizes a queue header associated with said queue to retrieve said entry from said queue.

Claim 41

A digital data processing system, comprising a plurality of nodes for performing processing tasks, and a central memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, each of said nodes comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data between said nodal memory and another node by generating an entry identifying a data buffer in said nodal memory, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to participate in a transfer of a block of data between said node and a data buffer identified in said entry, wherein said central memory comprises a queue buffer, said memory structures comprise queues located in said queue buffer, said queue buffer comprises a queue buffer header comprises a plurality of queue headers each associated with a node, and a queue buffer body comprising a plurality of queue entries, said queue headers and queue entries each comprise a node queue link field to facilitate linking of said queue headers and queue entries into queues, and each of said nodes that retrieves an entry from a queue in said central memory with which said node is associated utilizes a queue header associated with said queue to retrieve said entry from said queue.

Claim 42

A digital data processing system, comprising a plurality of nodes for performing processing tasks, one of said nodes being a host connected to every other node and having local access to a host memory, for creating in said host memory a plurality of memory structures for storing entries, each of said memory structures being associated with one of said nodes, and for performing other processing tasks, each of said nodes, including said host, comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data directly between said nodal memory to which said processor has local access and another node by generating an entry identifying a data buffer in said nodal memory to which said processor has local access, and by inserting said entry directly into a memory structure in said host memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said host memory with which said node comprising said processor is associated, and to particulate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access, each of said nodes other than said host being arranged to initiate a transfer of a block of data by inserting said entry directly into said memory structure without assistance from said host, thereby leaving said host free to perform other processing tasks and communicate with other nodes.

Claim 43

A digital data processing system, comprising a plurality of nodes for performing processing tasks, one of said nodes being a host connected to every other node and having local access to a host memory, for creating in said host memory a plurality of memory structures for storing entries, each of said memory structures being associated with one of said nodes, and for performing other processing tasks, each of said nodes, including said host, comprising a processor, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data directly between said nodal memory to which said processor has local access and another node by generating an entry identifying a data buffer in said nodal memory to which said processor has local access, and by inserting said entry directly into a memory structure in said host memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said host memory with which said node comprising said processor is associated, and to particulate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access, each of said nodes other than said host being arranged to initiate a transfer of a block of data by inserting said entry directly into said memory structure without assistance from said host, thereby leaving said host free to perform other processing tasks and communicate with other nodes.

Claim 44

A system as defined in claim 36 wherein said host is a said node arranged to initiate and participate in transfers of information.

Claim 45

A node for use in a digital data processing system comprising a plurality of nodes, one of said nodes being a host connected to every other node, said host having local access to a host memory and being arranged to initialize, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each of said memory structures being associated with one of said nodes, said node comprising a processor for performing processing tasks, and a nodal memory for storing information, said node being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks and communicate with other nodes, said node being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer compound contained in said entry, said host being arranged to initiate a transfer of information and to retrieve an entry from a memory structure in said host memory in the same manner as said node.

Claim 46

A node for use in a digital data processing system comprising a plurality of nodes, one of said nodes being a host connected to every other node, said host having local access to a host memory and being arranged to initialize, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each of said memory structures being associated with one of said nodes, said node comprising a processor for performing processing tasks, and a nodal memory for storing information, said node being arranged to initiate a transfer of information, by generating an entry containing an information transfer command, and by inserting said entry directly into a memory structure in said host memory associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks and communicate with other nodes, said node being arranged to retrieve an entry from a memory structure in said host memory with which said node is associated, and to participate in a transfer of information in accordance with an information transfer compound contained in said entry, said host being arranged to initiate a transfer of information and to retrieve an entry from a memory structure in said host memory in the same manner as said node.

Claim 47

A node for use in a digital data processing system comprising a central memory connected to a plurality of nodes, said central memory being arranged to store entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, said node comprising a processor for performing processing tasks, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data directly between said nodal memory to which said processor has local access and another node by generating an entry identifying a data buffer in said nodal memory to which said processor has local access, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to participate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access.

Claim 48

A node for use in a digital data processing system comprising a central memory connected to a plurality of nodes, said central memory being arranged to store entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, said node comprising a processor for performing processing tasks, and a nodal memory comprising at least one data buffer for storing a block of data, said processor having local access, exclusive of other processors in other nodes, to said nodal memory, said processor being arranged to initiate a transfer of a block of data directly between said nodal memory to which said processor has local access and another node by generating an entry identifying a data buffer in said nodal memory to which said processor has local access, and by inserting said entry into a memory structure in said central memory associated with said another node, said processor being arranged to retrieve an entry from a memory structure in said central memory with which said node comprising said processor is associated, and to participate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access.

Claim 49

A host for use in a digital data processing system comprising a plurality of nodes for performing processing tasks, said plurality of nodes comprising said host, said host comprising a host memory, and a host processor, connected to each of said nodes and having local access to said host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each of said memory structures being associated with one of said nodes, and for performing other processing tasks and communicating with other nodes, said host memory being arranged to receive and store an entry generated by a node in order to initiate a transfer of information, said entry containing an information transfer command, said host memory being arranged to enable said node to insert said entry directly into a memory structure associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks, said host memory being arranged to permit a node to retrieve an entry from a memory structure in said host memory with which said node is associated, in order to enable said node to participate in a transfer of information in accordance with an information transfer command contained in said entry, said host being arranged to initiate a transfer of information and to retrieve an entry from a memory structure in said host memory in the same manner as other nodes.

Claim 50

A host for use in a digital data processing system comprising a plurality of nodes for performing processing tasks, said plurality of nodes comprising said host, said host comprising a host memory, and a host processor, connected to each of said nodes and having local access to said host memory, for initializing, in said host memory, a plurality of memory structures for storing entries containing information transfer commands, each of said memory structures being associated with one of said nodes, and for performing other processing tasks and communicating with other nodes, said host memory being arranged to receive and store an entry generated by a node in order to initiate a transfer of information, said entry containing an information transfer command, said host memory being arranged to enable said node to insert said entry directly into a memory structure associated with another node without assistance from said host, thereby leaving said host free to perform other processing tasks, said host memory being arranged to permit a node to retrieve an entry from a memory structure in said host memory with which said node is associated, in order to enable said node to participate in a transfer of information in accordance with an information transfer command contained in said entry, said host being arranged to initiate a transfer of information and to retrieve an entry from a memory structure in said host memory in the same manner as other nodes.

Claim 51

A host for use in a digital data processing system comprising a plurality of nodes for performing processing tasks, each of said nodes having local access, exclusive of other nodes, to a respective one of a plurality of nodal memories, said host comprising a host memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, and a host processor for performing processing tasks, said host processor having local access to said host memory, said host memory being arranged to receive and store an entry generated by a node in order to initiate a transfer of a block of data directly between a nodal memory to which said node has local access and another node, said entry identifying a data buffer in said nodal memory to which said node has local access, said entry being inserted into a memory structure associated with said another node, said host memory being arranged to permit a node to retrieve an entry from a memory structure in said host memory with which said node is associated, in order to enable said node to participate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access.

Claim 52

A host for use in a digital data processing system comprising a plurality of nodes for performing processing tasks, each of said nodes having local access, exclusive of other nodes, to a respective one of a plurality of nodal memories, said host comprising a host memory for storing entries in a plurality of memory structures, each of said memory structures being associated with one of said nodes, and a host processor for performing processing tasks, said host processor having local access to said host memory, said host memory being arranged to receive and store an entry generated by a node in order to initiate a transfer of a block of data directly between a nodal memory to which said node has local access and another node, said entry identifying a data buffer in said nodal memory to which said node has local access, said entry being inserted into a memory structure associated with said another node, said host memory being arranged to permit a node to retrieve an entry from a memory structure in said host memory with which said node is associated, in order to enable said node to participate in a transfer of a block of data directly between said node and a data buffer identified in said entry and located in a nodal memory to which another node has local access.

Claim 53

A digital data processing system comprising a host connected to a plurality of nodes, said host including a queue buffer, the queue buffer including a plurality of queues with each queue being associated with a node, said plurality of nodes including a plurality of information buffers, each node comprising: A. destination node identification means for identifying a destination node to receive information; B. information transfer means connected to said information buffers for transferring information between a source information buffer and a destination information buffer; C. queue entry generation means, connected to said destination node identification means and said queue buffer, for generating a queue entry containing an information transfer command and for inserting said queue entry into said queue of said queue buffer associated with the identified destination queue; and D. queue entry processing means connected to said queue buffer for iteratively retrieving queue entries from the queue in said queue buffer associated with the node and for processing each retrieved queue entry, wherein said queue entry generation means includes: a. a queue entry selection portion for selecting a queue entry; b. a queue entry generation portion for loading an information transfer command in the queue entry selected by said queue selection portion; and c. a queue entry insertion portion for identifying a destination queue in said queue buffer associated with the identified destination node and for inserting the queue entry generated by said queue entry generating portion, said queue buffer comprises (i) a queue buffer header including a plurality of queue headers each associated with a node and (ii) a queue buffer body comprising a plurality of queue entries, the queue headers and queue entries each including a node queue link field to facilitate linking of said queue headers and queue entries into queues, said queue entry insertion portion using the queue header associated with the destination node in linking a queue entry generated by said queue entry generating portion to the queue associated with the destination node, and said queue buffer header further includes a free queue header including a free queue link field to facilitate linking of queue entries in said queue buffer body into a free queue, said queue entry selection portion selecting a queue entry from said free queue.

Claim 54

A digital data processing system comprising a host connected to a plurality of nodes, said host including a queue buffer, the queue buffer including a plurality of queues with each queue being associated with a node, said plurality of nodes including a plurality of information buffers, each node comprising: A. destination node identification means for identifying a destination node to receive information; B. information transfer means connected to said information buffers for transferring information between a source information buffer and a destination information buffer; C. queue entry generation means, connected to said destination node identification means and said queue buffer, for generating a queue entry containing an information transfer command and for inserting said queue entry into said queue of said queue buffer associated with the identified destination queue; and D. queue entry processing means connected to said queue buffer for iteratively retrieving queue entries from the queue in said queue buffer associated with the node and for processing each retrieved queue entry, wherein said queue entry generation means includes: a. a queue entry selection portion for selecting a queue entry; b. a queue entry generation portion for loading an information transfer command in the queue entry selected by said queue selection portion; and c. a queue entry insertion portion for identifying a destination queue in said queue buffer associated with the identified destination node and for inserting the queue entry generated by said queue entry generating portion, said queue buffer comprises (i) a queue buffer header including a plurality of queue headers each associated with a node and (ii) a queue buffer body comprising a plurality of queue entries, the queue headers and queue entries each including a node queue link field to facilitate linking of said queue headers and queue entries into queues, said queue entry insertion portion using the queue header associated with the destination node in linking a queue entry generated by said queue entry generating portion to the queue associated with the destination node, and said queue buffer header further includes a free queue header including a free queue link field to facilitate linking of queue entries in said queue buffer body into a free queue, said queue entry selection portion selecting a queue entry from said free queue.

Claim 55

A system as defined in claim 42 in which said queue entry selection portion comprises: A. a free queue header identification portion for identifying the free queue header; B. a free queue entry identification portion responsive to identification of the queue header by said queue header identification portion for using the node queue link fields of said identifies free queue header to locate a free queue entry in the free queue; and C. a queue entry unlinking portion for unlinking the free queue entry identified by said free queue entry identification portion.

Claim 56

A system as defined in claim 42 in which said queue buffer header includes a plurality of free queue headers each including a free queue link field to facilitate linking of queue entries into a like plurality of free queues, said host further including a system descriptor block for identifying a free queue for each node, said queue entry selection portion using the system descriptor block to identify a free queue from which it selects a queue entry.

Claim 57

A system as defined in claim 44 in which said queue entry selection portion comprises: A. a system descriptor block processor for processing said system descriptor block to identify a free queue associated with the destination node; B. a free queue header identification portion for identifying the free queue header associated with the identified free queue; C. a free queue entry identification portion responsive to identification of the queue header by said queue header identification portion for using the node queue link field of said identified free queue header to locate a free queue entry in the free queue; and D. a queue entry unlinking portion for unlinking the free queue entry identified by said free queue entry identification portion.

Claim 58

A system as defined in claim 45 in which said system descriptor block includes a plurality of node entries each associated with anode, each node entry identifying a free queue, said system descriptor block processor including: A. a node entry locator for locating the node entry in the system descriptor block associated with the destination node; and B. a free queue locator for locating a free queue identified by the node entry located by said node entry locator.

Claim 59

A system as defined in claim 46, each node entry in said system descriptor block including a free queue descriptor including (i) a first free queue pointer to a free queue header in said queue buffer header and (ii) a length indicator, said free queue locator comprising: A. a first free queue header locator responsive to said first fee queue pointer for locating the free queue header identified thereby; B. a free queue determination portion for determining whether an identified free queue includes free queue entries; C. a control portion for iteratively enabling said free queue determination portion, beginning with the free queue header identified by said first free queue header until either the free queue determination portion identifies a free queue that includes a free queue entry or until the number of iteration corresponds to the value identified by said length indicator.

Claim 60

A node for use in a digital data processing system comprising a host connected to a plurality of nodes, said host including a queue buffer, the queue buffer including a plurality of queues with each queue being associated with a node, said plurality of nodes including a plurality of information buffers, each node comprising: A. a destination node identification means for identifying a destination node to receive information; B. information transfer means for connection to said information buffers for transferring information between a source information buffer and a destination information buffer; and C. queue entry generation means connected to said destination node identification means and for connection to said queue buffer, for generating a queue entry containing an information transfer command and for inserting said queue entry into said queue of said queue buffer associated with the identified destination queue, wherein said queue entry generation means includes: a. a queue entry selection portion for selecting a queue entry; b. a queue entry generating portion for loading an information transfer command in the queue entry selected by said queue entry selection portion; and c. a queue entry insertion portion for identifying a destination queue in said queue buffer associated with the identified destination node and for inserting the queue entry generated by said queue entry generating portion, said queue buffer comprises (i) a queue buffer header including a plurality of queue headers each associated with a node and (ii) a queue buffer body comprising a plurality of queue entries, the queue headers and queue entries each including a node queue link field to facilitate linking of said queue headers and queue entries into queues, said queue entry insertion portion using the queue header associated with the destination node in linking a queue entry generated by said queue entry generating portion to the queue associated with the destination node, and said queue buffer header further includes a free queue header including a free queue link field to facilitate linking of queue entries in said queue buffer body into a free queue, said queue entry selection portion selecting a queue entry from said free queue.

Claim 61

A node for use in a digital data processing system comprising a host connected to a plurality of nodes, said host including a queue buffer, the queue buffer including a plurality of queues with each queue being associated with a node, said plurality of nodes including a plurality of information buffers, each node comprising: A. a destination node identification means for identifying a destination node to receive information; B. information transfer means for connection to said information buffers for transferring information between a source information buffer and a destination information buffer; and C. queue entry generation means connected to said destination node identification means and for connection to said queue buffer, for generating a queue entry containing an information transfer command and for inserting said queue entry into said queue of said queue buffer associated with the identified destination queue, wherein said queue entry generation means includes: a. a queue entry selection portion for selecting a queue entry; b. a queue entry generating portion for loading an information transfer command in the queue entry selected by said queue entry selection portion; and c. a queue entry insertion portion for identifying a destination queue in said queue buffer associated with the identified destination node and for inserting the queue entry generated by said queue entry generating portion, said queue buffer comprises (i) a queue buffer header including a plurality of queue headers each associated with a node and (ii) a queue buffer body comprising a plurality of queue entries, the queue headers and queue entries each including a node queue link field to facilitate linking of said queue headers and queue entries into queues, said queue entry insertion portion using the queue header associated with the destination node in linking a queue entry generated by said queue entry generating portion to the queue associated with the destination node, and said queue buffer header further includes a free queue header including a free queue link field to facilitate linking of queue entries in said queue buffer body into a free queue, said queue entry selection portion selecting a queue entry from said free queue.

Claim 62

A node as defined in claim 48 in which said queue entry selection portion comprises: A. a free queue header identification portion for identifying the free queue header; B. a free queue entry identification portion responsive to identification of the queue header by said queue header identification portion for using the node queue link fields of said identified free queue header to locate a free queue entry in the free queue; and C. a queue entry unlinking portion for unlinking the free queue entry identified by said free queue entry identification portion.

Claim 63

A node as defined in claim 48 in which said queue buffer header includes a plurality of free queue headers each including a free queue link field to facilitate linking of queue entries into a like plurality of free queues, said host further including a system descriptor block for identifying a free queue for each node, said queue entry selection portion using the system descriptor block to identify a free queue from which it selects a queue entry.

Claim 64

A node as defined in claim 50 in which said queue entry selection portion comprises: A. a system descriptor block processor for processing said system descriptor block to identify a free queue associated with the destination node; B. a free queue header identification portion for identifying the free queue header associated with the identified free queue; C. a free queue entry identification portion responsive to identification of the queue header by said queue header identification portion for using the node queue link fields of said identified free queue header to locate a free queue entry in the free queue; and D. a queue entry unlinking portion for unlinking the free queue entry identified by said free queue entry identification portion.

Claim 65

A node as defined in claim 51 in which said system descriptor block includes a plurality of node entries each associated with a node, each node entry identifying a free queue, said system descriptor block processor including: A. a node entry locator for locating the node entry in the system descriptor block associated with the destination node; and B. a free queue locator for locating a free queue identified by the node entry located by said node entry locator.

Claim 66

A node as defined in claim 52, each node entry in said system descriptor block including a free queue descriptor including (i) a first free queue pointer to a free queue header in said queue buffer header and (ii) a length indicator, said free queue locator comprising: A. a first fee queue header locator responsive to said first free queue pointer for locating the free queue header identified thereby; B. a free queue determination portion for determining whether an identified free queue includes free queue entries; C. a control portion for iteratively enabling said free queue determination portion, beginning with the free queue header identified by said first free queue header until either the free queue determination portion identifies a free queue that includes a free queue entry of until the number of iterations corresponds to the value identified by said length indicator.