US4447874A
Expired / Lapsed
US
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Apparatus and method for communication of information between processes in an information system
Assignee: Bull SAS
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Filing: 1981-04-14
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Granted: 1984-05-08
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Expires: 2001-04-14
Abstract
Abstract An apparatus for enabling communication of information between processes being carried out on a computing system. Each process is assigned a control block including a specialized memory element. A process being executed modifies the state of each memory element if it discovers any information of interest to processes awaiting execution. Before the next process is executed, the memory element in its control block is tested to find out if the previously-executed process left any information of interest.
Inventors
- 👤 John J. Bradley
- 👤 Benjamin S. Franklin
- 👤 David M. Slosberg
- 👤 Marc Appell
- 👤 Jean-Claude Cassonnet
- 👤 Philippe D. De Sabatier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/54; G06F12/00; G06F12/14; G06F12/1458; G06F12/1491; G06F9/461; G06F9/463
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
209 words
In a computing system capable of processing a plurality of processes including central memory means for storing a process control block for each of the processes, means for operating the processes in queues, central processor means for executing one of the processes during a predetermined time and for maintaining the unexecuted processes in queues located in the central memory means, said unexecuted queues being organized by priority into various states of readiness for execution, distributor means for giving command of the central processor means to the one of the processes having the highest priority, and means for assigning to each of the processes a process ring number symbolizing a priority level, improved apparatus for communicating instructions between at least some of the processes comprising: memory element means located in each process control block for storing information; means responsive to the process being executed for modifying the information stored in the memory element means associated with processes to which instructions are to be communicated; interrupt means responsive to the information stored in the memory element means for causing an interrupt; and exceptions means responsive to the interrupt for enabling the instruction to be communicated to each process corresponding to a memory element means in which the modified information was stored.
Claim 2
Dependent Claim
209 words
In a computing system capable of processing a plurality of processes including central memory means for storing a process control block for each of the processes, means for operating the processes in queues, central processor means for executing one of the processes during a predetermined time and for maintaining the unexecuted processes in queues located in the central memory means, said unexecuted queues being organized by priority into various states of readiness for execution, distributor means for giving command of the central processor means to the one of the processes having the highest priority, and means for assigning to each of the processes a process ring number symbolizing a priority level, improved apparatus for communicating instructions between at least some of the processes comprising: memory element means located in each process control block for storing information; means responsive to the process being executed for modifying the information stored in the memory element means associated with processes to which instructions are to be communicated; interrupt means responsive to the information stored in the memory element means for causing an interrupt; and exceptions means responsive to the interrupt for enabling the instruction to be communicated to each process corresponding to a memory element means in which the modified information was stored.
Claim 3
Dependent Claim
30 words
Apparatus, as in claim 1, wherein the interrupt means is responsive to the modified information every time the distributor means assigns control of the central processor means to another process.
Claim 4
Dependent Claim
87 words
Apparatus, as in claim 1, wherein the processes have priority levels determined by the nature of operations being carried out, the priority levels being defined by ring numbers associated with respective processes; means for testing the memory element means and for thereafter testing the number of the ring in which the process is being executed, the interrupt means responsive to said testing means to cause an interrupt only in response to the tested process ring number being greater than or equal to a predetermined alarm ring number.
Claim 5
Dependent Claim
37 words
Apparatus, as in claim 3, wherein the means for testing the memory element means is activated during execution of an output instruction by the central processor means in response to a process being changed while being executed.
Claim 6
Dependent Claim
204 words
In a computing system capable of processing a plurality of processes including central memory means for storing a process control block for each of the processes, means for operating the processes in central queues, processor means for executing one of the processes during a predetermined time and for maintaining the unexecuted processes in queues located in the central memory means, said queues being organized by priority into various states of readiness for execution, distributor means for giving command of the central processor means to the one of the processes having the highest priority, and means for assigning to each of the processes a process ring number symbolizing a priority level, a method of communicating instructions between at least some of the processes comprising the steps of: storing information in a memory element means located in each process control block; executing the process being executed to modify the information stored in the memory element means associated with the process to which instructions are to be communicated; causing an interrupt in response to the information stored in the memory element means; and in response to the interrupt, communicating the instruction to each process corresponding to a memory element means in which the modified information was stored.
Claim 7
Dependent Claim
204 words
In a computing system capable of processing a plurality of processes including central memory means for storing a process control block for each of the processes, means for operating the processes in central queues, processor means for executing one of the processes during a predetermined time and for maintaining the unexecuted processes in queues located in the central memory means, said queues being organized by priority into various states of readiness for execution, distributor means for giving command of the central processor means to the one of the processes having the highest priority, and means for assigning to each of the processes a process ring number symbolizing a priority level, a method of communicating instructions between at least some of the processes comprising the steps of: storing information in a memory element means located in each process control block; executing the process being executed to modify the information stored in the memory element means associated with the process to which instructions are to be communicated; causing an interrupt in response to the information stored in the memory element means; and in response to the interrupt, communicating the instruction to each process corresponding to a memory element means in which the modified information was stored.
Claim 8
Dependent Claim
30 words
The method of claim 5, wherein the interrupt means is responsive to the modified information every time the distributor means assigns control of the central processor means to another process.
Claim 9
Dependent Claim
77 words
The method of claim 5, including the additional steps of: generating a priority level defined by the ring number in response to a function of the nature of the operations being carried out; and testing the memory element means and thereafter testing the number of the ring in which the process is being executed, the interrupt ring caused only in response to the process ring number being greater than or equal to a predetermined alarm ring number.
Claim 10
Dependent Claim
33 words
The method of claim 7, wherein the testing step is carried out during execution of an output instruction by the central processing means in response to a process ring changed while being executed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-08 | 1987-11-07 | 1988-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-08 | 1991-11-07 | 1992-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-08 | 1995-11-07 | 1996-05-08 | $7700.00 | Window Closed / Lapsed |