US5136382A
Expired / Lapsed
US
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Video signal digital slicing circuit
Assignee: STMicroelectronics SA
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Filing: 1990-10-02
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Granted: 1992-08-04
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Expires: 2010-10-02
Abstract
Abstract An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (VT).
Inventors
- 👤 Jacques Meyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:29
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/08; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/046; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/086; H03K5/088; H04N7/025; H04N7/035; H04N7/0355
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
187 words
An extractor for digital data transmitted at a first determined frequency (fo) through a video channel after an input signal including a burst of Os and 1s is emitted at said first frequency (fo) onto a first input (VIN) of a comparator (1) for comparing said input signal with a threshold level, the extractor including means for supplying a second frequency (F0) as a multiple by N of the first frequency (fo), and means for supplying said threshold level, operating during said burst duration, wherein the means for supplying the threshold level comprises: an up/down counter (12) operating at said multiple frequency (F0), the counter including an up/down counting input connected to an output of said comparator (1), and a digital/analog converter (16) receiving an output of the up/down counter and supplying said threshold level (VT); and wherein the comparator output is connected to an edge detector (24) acting, during said burst, on a divider by N (20) of the second frequency (F0) for supplying to a flip-flop (2), connected to the comparator output, a clock signal at the first frequency (fo) with a desired phase relationship.
Claim 2
Dependent Claim
187 words
An extractor for digital data transmitted at a first determined frequency (fo) through a video channel after an input signal including a burst of Os and 1s is emitted at said first frequency (fo) onto a first input (VIN) of a comparator (1) for comparing said input signal with a threshold level, the extractor including means for supplying a second frequency (F0) as a multiple by N of the first frequency (fo), and means for supplying said threshold level, operating during said burst duration, wherein the means for supplying the threshold level comprises: an up/down counter (12) operating at said multiple frequency (F0), the counter including an up/down counting input connected to an output of said comparator (1), and a digital/analog converter (16) receiving an output of the up/down counter and supplying said threshold level (VT); and wherein the comparator output is connected to an edge detector (24) acting, during said burst, on a divider by N (20) of the second frequency (F0) for supplying to a flip-flop (2), connected to the comparator output, a clock signal at the first frequency (fo) with a desired phase relationship.
Claim 3
Dependent Claim
18 words
A digital data extractor according to claim 1, wherein the digital/analog converter (16) is of an exponential type.
Claim 4
Dependent Claim
25 words
A digital data extractor according to claim 1, wherein the comparator output is connected to a digital filter of a majority detection type (6, 8).
Claim 5
Dependent Claim
77 words
A digital data extractor according to claim 1, further including phasing means for establishing during said burst a predetermined phase for said clock signal relative to the output of said comparator, said phasing means comprising said edge detector, said flip-flop and said divider by N, said clock signal derived by said divider by N from said second frequency, said flip-flop sampling the output of said comparator at said first determined frequency (fo) and at said predetermined phase.
Claim 6
Dependent Claim
251 words
An extractor for digital data transmitted at a first predetermined frequency (fo) through a video channel after an input signal including a burst of 0s and 1s is emitted at said first frequency (fo), including: a comparator (1) for comparing said input signal with a threshold level, said comparator having a first input (VIN) receiving the digital data and the burst of 0s and 1s; means for supplying a second frequency (F0) as a multiple by N of the first frequency (fo), and means for supplying said threshold level, operating during said burst duration; said means for supplying the threshold level comprising: an up/down counter (12) operating at said multiple frequency (F0), the counter including an up/down counting input connected to an output of said comparator (1); and a digital/analog converter (16) receiving an output of the up/down counter and supplying said threshold level (VT); and further including phasing means for establishing a predetermined phase for a sampling signal derived from said second frequency, said phasing means comprising: an edge detector (24) connected to receive the output of said comparator; a divider by N (20) operating on the second frequency (F0), said divider by N responsive to an output of said edge detector; means for providing the output of said edge detector to said divider by N only during said burst; and a flip-flop (2) connected for sampling the comparator output, said flip-flop receiving from said divider by N a sampling signal having said predetermined phase at the first frequency (fo).
Claim 7
Dependent Claim
251 words
An extractor for digital data transmitted at a first predetermined frequency (fo) through a video channel after an input signal including a burst of 0s and 1s is emitted at said first frequency (fo), including: a comparator (1) for comparing said input signal with a threshold level, said comparator having a first input (VIN) receiving the digital data and the burst of 0s and 1s; means for supplying a second frequency (F0) as a multiple by N of the first frequency (fo), and means for supplying said threshold level, operating during said burst duration; said means for supplying the threshold level comprising: an up/down counter (12) operating at said multiple frequency (F0), the counter including an up/down counting input connected to an output of said comparator (1); and a digital/analog converter (16) receiving an output of the up/down counter and supplying said threshold level (VT); and further including phasing means for establishing a predetermined phase for a sampling signal derived from said second frequency, said phasing means comprising: an edge detector (24) connected to receive the output of said comparator; a divider by N (20) operating on the second frequency (F0), said divider by N responsive to an output of said edge detector; means for providing the output of said edge detector to said divider by N only during said burst; and a flip-flop (2) connected for sampling the comparator output, said flip-flop receiving from said divider by N a sampling signal having said predetermined phase at the first frequency (fo).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-04 | 1996-02-03 | 1996-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-04 | 2000-02-03 | 2000-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-04 | 2004-02-03 | 2004-08-04 | $7700.00 | Window Closed / Lapsed |