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US5134399A
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Subranging analog-to-digital converter with dither
Assignee: Agilent Technologies Inc
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Filing: 1990-10-05
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Granted: 1992-07-28
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Expires: 2010-10-05
Abstract
Abstract Noise (dither) is introduced into a subranging analog-to-digital converter to enhance conversion accuracy. The resolution of the noise is sufficiently fine that its least significant bits can be changed without always changing the second pass approximation from the converter's internal analog-to-digital converter. Additional bits of statistical resolution can thereby be achieved without sacrificing the overlap between the dither word and the first pass digital approximation that is needed to provide dithered error correction.
Inventors
- 👤 Donald R. Hiller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:21
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/20; H03M1/201; H03M1/14; H03M1/144
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
65 words
In a multi-pass analog-to-digital conversion method that includes introducing an M-bit dither word into a first digital approximation, producing an analog residue signal from said approximation, and using an analog-to-digital converter to produce a second digital approximation from the residue signal, an improvement comprising the step of toggling the least significant bit of M-bit dither word without changing any bits of the second digital approximation.
Claim 2
Dependent Claim
65 words
In a multi-pass analog-to-digital conversion method that includes introducing an M-bit dither word into a first digital approximation, producing an analog residue signal from said approximation, and using an analog-to-digital converter to produce a second digital approximation from the residue signal, an improvement comprising the step of toggling the least significant bit of M-bit dither word without changing any bits of the second digital approximation.
Claim 3
Dependent Claim
31 words
The method of claim 1 which further includes the step of changing the two least significant bits of the M-bit dither word without changing any bits of the second digital approximation.
Claim 4
Dependent Claim
31 words
The method of claim 1 which further includes the step of changing the three least significant bits of the M-bit dither word without changing any bits of the second digital approximation.
Claim 5
Independent Claim
224 words
A method of analog-to-digital conversion comprising the steps: scaling an analog input signal by a factor of K; converting the scaled analog input signal into an N 1 -bit digital word approximately corresponding thereto; providing a pseudo-random signal comprised of M-bit digital noise words; justifying the N 1 -bit digital word as the most significant bits of a P-bit digital word; justifying one of the M-bit digital noise words as the least significant bits of the P-bit word and summing said justified M-bit digital noise word with said justified N 1 -bit word to produce a composite P-bit word with dither; producing an analog signal corresponding to the P-bit word; subtracting the analog signal corresponding to the P-bit word from the input analog signal to yield an analog residue signal; scaling the analog residue signal by a factor of L, where the ratio L/K is an integral power of two; converting the amplified analog residue signal into a N 2 -bit digital word approximately corresponding thereto; justifying the P-bit word as the most significant bits of an output word; justifying the N 2 -bit digital word so the least significant bit thereof occupies bit X+1 of the output word, and summing said justified N 2 -bit word with said justified P-bit word to produce a composite output word; wherein: X=P-N.sub.2 -log.sub.2 (L/K), and X≧1.
Claim 6
Independent Claim
224 words
A method of analog-to-digital conversion comprising the steps: scaling an analog input signal by a factor of K; converting the scaled analog input signal into an N 1 -bit digital word approximately corresponding thereto; providing a pseudo-random signal comprised of M-bit digital noise words; justifying the N 1 -bit digital word as the most significant bits of a P-bit digital word; justifying one of the M-bit digital noise words as the least significant bits of the P-bit word and summing said justified M-bit digital noise word with said justified N 1 -bit word to produce a composite P-bit word with dither; producing an analog signal corresponding to the P-bit word; subtracting the analog signal corresponding to the P-bit word from the input analog signal to yield an analog residue signal; scaling the analog residue signal by a factor of L, where the ratio L/K is an integral power of two; converting the amplified analog residue signal into a N 2 -bit digital word approximately corresponding thereto; justifying the P-bit word as the most significant bits of an output word; justifying the N 2 -bit digital word so the least significant bit thereof occupies bit X+1 of the output word, and summing said justified N 2 -bit word with said justified P-bit word to produce a composite output word; wherein: X=P-N.sub.2 -log.sub.2 (L/K), and X≧1.
Claim 7
Dependent Claim
8 words
The method of claim 4 in which X=3.
Claim 8
Dependent Claim
15 words
The method of claim 5 in which P=16, N 2 =8, and log 2 (L/K)=5.
Claim 9
Dependent Claim
8 words
The method of claim 6 in which M=9.
Claim 10
Dependent Claim
205 words
An analog-to-digital converter comprising: an input for receiving an input analog signal; first scaling means coupled to the input for scaling the input analog signal by a factor of K to produce a scaled analog input signal; an analog-to-digital converter coupled to the first scaling means for converting the scaled analog input signal into an N-bit digital word approximately corresponding thereto; a noise source of M-bit digital noise words; a first P-bit accumulator having inputs coupled to the noise source and to the analog-to-digital converter; a P-bit latch circuit coupled to an output of the P-bit accumulator; a digital-to-analog converter for converting an output signal from the latch into an analog signal corresponding thereto; a subtraction circuit for subtracting the analog signal from the digital-to-analog converter from the input analog signal to yield an analog residue signal; second scaling means coupled to the subtraction circuit for scaling the analog residue signal by a factor of L, where the ratio L/K is an integral power of two, said second scaling means having an output coupled to the analog-to-digital converter; a second P-bit accumulator having a first input connected to the analog-to-digital converter and having a second input connected to the P-bit latch circuit; wherein: P-N-log.sub.2 (L/K)≦1.
Claim 11
Dependent Claim
205 words
An analog-to-digital converter comprising: an input for receiving an input analog signal; first scaling means coupled to the input for scaling the input analog signal by a factor of K to produce a scaled analog input signal; an analog-to-digital converter coupled to the first scaling means for converting the scaled analog input signal into an N-bit digital word approximately corresponding thereto; a noise source of M-bit digital noise words; a first P-bit accumulator having inputs coupled to the noise source and to the analog-to-digital converter; a P-bit latch circuit coupled to an output of the P-bit accumulator; a digital-to-analog converter for converting an output signal from the latch into an analog signal corresponding thereto; a subtraction circuit for subtracting the analog signal from the digital-to-analog converter from the input analog signal to yield an analog residue signal; second scaling means coupled to the subtraction circuit for scaling the analog residue signal by a factor of L, where the ratio L/K is an integral power of two, said second scaling means having an output coupled to the analog-to-digital converter; a second P-bit accumulator having a first input connected to the analog-to-digital converter and having a second input connected to the P-bit latch circuit; wherein: P-N-log.sub.2 (L/K)≦1.
Claim 12
Dependent Claim
164 words
In a multi-pass analog-to-digital conversion method, wherein output bits of first and second conversion passes overlap, that includes using an analog-to-digital converter to produce a first N 1 -bit digital approximation from an input signal in a first pass, summing an M-bit dither word with the first N 1 -bit digital approximation to yield a P-bit intermediate result, producing an analog residue signal from said intermediate result, amplifying the analog residue signal by 2K relative to the first pass where k<N 1 , using an analog-to-digital converter to produce a second N 2 -bit digital approximation from the amplified residue signal, and combining the second N 2 -bit digital approximation with P-bit intermediate result to yield a Q-bit final output word, an improvement wherein one or more of least significant bits of the M-bit dither word are of such fine resolution that, despite the bit overlap, Q=N 1 +N 2 , where N 1 , N 2 , M, P and Q are integers.
Claim 13
Dependent Claim
164 words
In a multi-pass analog-to-digital conversion method, wherein output bits of first and second conversion passes overlap, that includes using an analog-to-digital converter to produce a first N 1 -bit digital approximation from an input signal in a first pass, summing an M-bit dither word with the first N 1 -bit digital approximation to yield a P-bit intermediate result, producing an analog residue signal from said intermediate result, amplifying the analog residue signal by 2K relative to the first pass where k<N 1 , using an analog-to-digital converter to produce a second N 2 -bit digital approximation from the amplified residue signal, and combining the second N 2 -bit digital approximation with P-bit intermediate result to yield a Q-bit final output word, an improvement wherein one or more of least significant bits of the M-bit dither word are of such fine resolution that, despite the bit overlap, Q=N 1 +N 2 , where N 1 , N 2 , M, P and Q are integers.
Claim 14
Dependent Claim
8 words
The method of claim 9 in which Q=P.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-28 | 1996-01-27 | 1996-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-28 | 2000-01-27 | 2000-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-28 | 2004-01-27 | 2004-07-28 | $7700.00 | Window Closed / Lapsed |