Co-processor for control setting an internal flag register operation mode which controlled a main processor execution mode in a multi-processor system

Claim 2

In a multi-processor system which includes a co-processor which executes operations instructed by a main processor using one or more internal registers incorporated in said co-processor, said co-processor comprising: (a) mode display means indicating one of a first mode or a second mode in accordance with one of a first request or a second request selectively input from said main processor; and (b) initialization control means, operatively interconnected to said one or more internal registers and to said mode display means, which does not initialize said one or more internal registers when said mode display means indicates said first mode at a time of completion of each of said operations, and initializes said one or more internal registers when said mode display means indicates said second mode at a time of completion of each of said operations.

Claim 3

A process performed by a multiprocessor system comprising the following steps: (a) checking a request line between a main processor and a co-processor to determine whether a main processor instruction sent from said main processor to said co-processor is a mode-setting instruction or a mode-resetting instruction; (b) setting a debugging mode flag register in said co-processor if said main processor instruction is said mode-setting instruction or said mode-resetting instruction; (c) determining if said main processor instruction is a register dumping instruction if said main processor instruction is not said mode-setting instruction or said mode-resetting instruction; (d) storing contents of internal registers in said co-processor in a saving area of a main memory if said main processor instruction is a register dumping instruction; and (e) executing said main processor instruction as an arithmetic instruction and clearing said internal registers if a debugging flag is in an OFF state if said main processor instruction is neither said register dumping instruction, nor said mode-setting instruction or said mode-resetting instruction.

Claim 4

A process performed by a multiprocessor system comprising the following steps: (a) checking a request line between a main processor and a co-processor to determine whether a main processor instruction sent from said main processor to said co-processor is a mode-setting instruction or a mode-resetting instruction; (b) setting a debugging mode flag register in said co-processor if said main processor instruction is said mode-setting instruction or said mode-resetting instruction; (c) determining if said main processor instruction is a register dumping instruction if said main processor instruction is not said mode-setting instruction or said mode-resetting instruction; (d) storing contents of internal registers in said co-processor in a saving area of a main memory if said main processor instruction is a register dumping instruction; and (e) executing said main processor instruction as an arithmetic instruction and clearing said internal registers if a debugging flag is in an OFF state if said main processor instruction is neither said register dumping instruction, nor said mode-setting instruction or said mode-resetting instruction.