Resonant-transition DC-to-DC converter

Claim 2

A full bridge, resonant transition, DC-to-DC, switching power converter circuit, adapted to be used with a DC power supply means, which circuit comprises: (a) a bridge circuit having a separate switch connected in each of the four legs thereof, and adapted so that said DC power supply means can be connected across a first diagonal of said bridge circuit; (b) a power transformer having a primary winding, a first secondary winding and a second secondary winding, said first and second secondary windings being connected in a center-tapped configuration, and said primary winding being connected across a second diagonal of said bridge circuit; (c) means for determining and controlling a conduction interval for each of said switches to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, (d) a first saturable reactor, having a high impedance state and a saturated state, connected in series with said first secondary winding; (e) a first rectifier having an anode and a cathode, said anode being connected to said first saturable reactor; (f) a second saturable reactor, having a high impedance state and a saturated state, connected in series with said second secondary winding; and (g) a second rectifier having an anode and a cathode, said anode being connected to said second saturable reactor, and said cathode being connected to said cathode of said first rectifier, wherein said second saturable reactor is in said high impedance state for at least a portion of said first half-cycle free-wheeling interval, and said first saturable reactor is in said high impedance state for at least a portion of said second half-cycle free-wheeling interval.

Claim 3

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 1, wherein each said switch is a field effect transistor.

Claim 4

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 2, further comprising an inductor serially connected between said cathodes of said rectifiers and a converter output terminal.

Claim 5

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 3, wherein said first and second saturable reactors comprise a core of soft magnetic material.

Claim 6

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 3, wherein said first and second saturable reactors comprise a core of square BH loop magnetic material.

Claim 7

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 5, further comprising a reactor reset circuit.

Claim 8

A full bridge, resonant transition, switching power converter circuit comprising: (a) a bridge switching circuit for producing a chopped voltage from a DC input voltage, said switching circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, said first and second input terminals being adapted for connection to a DC input voltage, said switching circuit including (i) a first FET (Q1) having a parasitic drain source capacitor C1, Q1 being connected between said first input terminal and said first output terminal, (ii) a second FET (Q2) having a parasitic drain source capacitor C2, Q2 being connected between said second input terminal and said first output terminal, (iii) a third FET (Q3) having a parasitic drain source capacitor C3, Q3 being connected between said first input terminal and said second output terminal, and (iv) a fourth FET (Q4) having a parasitic drain source capacitor C4, Q4 being connected between said second input terminal and said second output terminal; (b) a power transformer having a primary winding, a first secondary winding, and a second secondary winding, said primary winding is connected across said first and second output terminals of said switching circuit, and said first and second secondary windings are connected in a center-tapped configuration; (c) a first saturable reactor connected in series with said first secondary winding, said first saturable reactor having a high impedance state and a saturated state; (d) a first rectifier having an anode and a cathode, said anode being connected to said first saturable reactor; (e) a second saturable reactor connected in series with said second secondary winding, said second saturable reactor having a high impedance state and a saturated state; (f) a second rectifier having an anode and a cathode, said anode being connected to said second saturable reactor, said cathode of said first rectifier being connected to said cathode of said second rectifier; (g) a filter inductor connected between the junction of said cathodes of said rectifiers and an output terminal of the power converter circuit; and (h) means for determining and controlling a conduction interval for each of Q1-Q4 to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, whereby during said first half-cycle freewheeling interval, said first saturable reactor is in said saturated state while said second saturable reactor is in said high impedance state, and during said second half-cycle freewheeling interval, said first saturable reactor is in said high impedance state while said second saturable reactor is in said saturated state, and whereby a current is induced to flow in T1 P during each free-wheeling interval.

Claim 9

A full bridge, resonant transition, switching power converter circuit comprising: (a) a bridge switching circuit for producing a chopped voltage from a DC input voltage, said switching circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, said first and second input terminals being adapted for connection to a DC input voltage, said switching circuit including (i) a first FET (Q1) having a parasitic drain source capacitor C1, Q1 being connected between said first input terminal and said first output terminal, (ii) a second FET (Q2) having a parasitic drain source capacitor C2, Q2 being connected between said second input terminal and said first output terminal, (iii) a third FET (Q3) having a parasitic drain source capacitor C3, Q3 being connected between said first input terminal and said second output terminal, and (iv) a fourth FET (Q4) having a parasitic drain source capacitor C4, Q4 being connected between said second input terminal and said second output terminal; (b) a power transformer having a primary winding, a first secondary winding, and a second secondary winding, said primary winding is connected across said first and second output terminals of said switching circuit, and said first and second secondary windings are connected in a center-tapped configuration; (c) a first saturable reactor connected in series with said first secondary winding, said first saturable reactor having a high impedance state and a saturated state; (d) a first rectifier having an anode and a cathode, said anode being connected to said first saturable reactor; (e) a second saturable reactor connected in series with said second secondary winding, said second saturable reactor having a high impedance state and a saturated state; (f) a second rectifier having an anode and a cathode, said anode being connected to said second saturable reactor, said cathode of said first rectifier being connected to said cathode of said second rectifier; (g) a filter inductor connected between the junction of said cathodes of said rectifiers and an output terminal of the power converter circuit; and (h) means for determining and controlling a conduction interval for each of Q1-Q4 to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, whereby during said first half-cycle freewheeling interval, said first saturable reactor is in said saturated state while said second saturable reactor is in said high impedance state, and during said second half-cycle freewheeling interval, said first saturable reactor is in said high impedance state while said second saturable reactor is in said saturated state, and whereby a current is induced to flow in T1 P during each free-wheeling interval.

Claim 10

The full bridge, resonant transition, switching power converter circuit set forth in claim 7, wherein said first and second saturable reactors each comprise a core of soft magnetic material.

Claim 11

The full bridge, resonant transition, switching power converter circuit set forth in claim 7, wherein said first and second saturable reactors each comprise a core of square BH loop magnetic material.

Claim 12

The full bridge, resonant transition, switching power converter circuit set forth in claim 9, further comprising a reactor reset circuit.

Claim 13

A full bridge, resonant transition, DC-to-DC, switching power converter circuit comprising: (a) a transformer having a primary winding, a first secondary winding and a second secondary winding; (b) full bridge switching means for chopping a DC voltage, said switching means adapted to provide a chopped voltage to said primary winding of said transformer; (c) means for controlling said switching means to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, (d) first blocking means for providing a blocking impedance in series with said first secondary of said transformer for at least a portion of said second half-cycle free-wheeling interval; and (e) second blocking means for providing a blocking impedance in series with said second secondary of said transformer for at least a portion of said first half-cycle free-wheeling interval.

Claim 14

A full bridge, resonant transition, DC-to-DC, switching power converter circuit comprising: (a) a transformer having a primary winding, a first secondary winding and a second secondary winding; (b) full bridge switching means for chopping a DC voltage, said switching means adapted to provide a chopped voltage to said primary winding of said transformer; (c) means for controlling said switching means to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, (d) first blocking means for providing a blocking impedance in series with said first secondary of said transformer for at least a portion of said second half-cycle free-wheeling interval; and (e) second blocking means for providing a blocking impedance in series with said second secondary of said transformer for at least a portion of said first half-cycle free-wheeling interval.

Claim 15

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 11, wherein each said blocking means includes a saturable reactor.

Claim 16

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 12, wherein said saturable reactors comprise a core of soft magnetic material.

Claim 17

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 12, wherein said saturable reactors comprise a core of square BH loop magnetic material.

Claim 18

The full bridge, resonant transition, DC-to-DC, switching power converter circuit set forth in claim 14, further comprising a reactor reset circuit.

Claim 19

In a full bridge, resonant transition, DC-to-DC, switching power converter circuit including: a bridge switching circuit for producing a chopped voltage from a DC input, said switching circuit having first and second input terminals adapted for connection to a DC input voltage and first and second output terminals, said switching circuit including a first FET (Q1) having a parasitic drain source capacitor C1, Q1 being connected between said first input terminal and said first output terminal, a second FET (Q2) having a parasitic drain source capacitor C2, Q2 being connected between said second input terminal and said first output terminal, a third FET (Q3) having a parasitic drain source capacitor C3, Q3 being connected between said first input terminal and said second output terminal, and a fourth FET (Q4) having a parasitic drain source capacitor C4, Q4 being connected between said second input terminal and said second output terminal; a power transformer having a primary winding, a first secondary winding, and a second secondary winding, said primary winding is connected across said first and second output terminals of said switching circuit, and said first and second secondary windings are connected in a center-tapped configuration; a first saturable reactor connected in series with said first secondary winding, said first saturable reactor having a high impedance state and a saturated state; a first rectifier having an anode and a cathode, said anode being connected to said first saturable reactor; a second saturable reactor connected in series with said second secondary winding, said second saturable reactor having a high impedance state and a saturated state; a second rectifier having an anode and a cathode, said anode being connected to said second saturable reactor, said cathode of said first rectifier being connected to said cathode of said second rectifier; a filter inductor connected between the junction of said cathodes of said rectifiers and an output terminal of the power converter circuit; and means for determining a conduction interval for and for controlling each of Q1-Q4 to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, a method for reducing switching power losses, said method including the steps of: (a) switching Q1 ON at a time t 1 to commence said first half-cycle on-time, Q4 is ON from a previous cycle of operation and Q2 and Q3 are OFF (b) switching Q4 OFF at a time t 2 to commence said first half-cycle free-wheeling interval; (c) maintaining SR2 in said high impedance state for at least a portion of said first half-cycle freewheeling interval; (d) switching Q3 ON at a time t 3 when the voltage across C3 reaches a desired level; (e) switching Q1 OFF at a time t 4 ; (f) switching Q2 ON at a time t 5 when the voltage across C2 reaches a desired level to commence said second half-cycle on-time; (g) switching Q3 OFF at a time t 6 to commence said second half-cycle free-wheeling interval; (h) maintaining SR1 in said high impedance state for at least a portion of said second half-cycle free-wheeling interval; (i) switching Q4 ON at a time t 7 when the voltage across C4 reaches a desired level; (j) switching Q2 OFF at a time t 8 ; and (k) switching Q1 ON at a time t 9 when the voltage across C1 reaches a desired level to recommence said first half-cycle on-time and to commence a next cycle of converter operation.

Claim 20

In a full bridge, resonant transition, DC-to-DC, switching power converter circuit including: a bridge switching circuit for producing a chopped voltage from a DC input, said switching circuit having first and second input terminals adapted for connection to a DC input voltage and first and second output terminals, said switching circuit including a first FET (Q1) having a parasitic drain source capacitor C1, Q1 being connected between said first input terminal and said first output terminal, a second FET (Q2) having a parasitic drain source capacitor C2, Q2 being connected between said second input terminal and said first output terminal, a third FET (Q3) having a parasitic drain source capacitor C3, Q3 being connected between said first input terminal and said second output terminal, and a fourth FET (Q4) having a parasitic drain source capacitor C4, Q4 being connected between said second input terminal and said second output terminal; a power transformer having a primary winding, a first secondary winding, and a second secondary winding, said primary winding is connected across said first and second output terminals of said switching circuit, and said first and second secondary windings are connected in a center-tapped configuration; a first saturable reactor connected in series with said first secondary winding, said first saturable reactor having a high impedance state and a saturated state; a first rectifier having an anode and a cathode, said anode being connected to said first saturable reactor; a second saturable reactor connected in series with said second secondary winding, said second saturable reactor having a high impedance state and a saturated state; a second rectifier having an anode and a cathode, said anode being connected to said second saturable reactor, said cathode of said first rectifier being connected to said cathode of said second rectifier; a filter inductor connected between the junction of said cathodes of said rectifiers and an output terminal of the power converter circuit; and means for determining a conduction interval for and for controlling each of Q1-Q4 to produce a first half-cycle and a second half-cycle of converter operation, said first and second half-cycles each including an on-time and a free-wheeling interval, a method for reducing switching power losses, said method including the steps of: (a) switching Q1 ON at a time t 1 to commence said first half-cycle on-time, Q4 is ON from a previous cycle of operation and Q2 and Q3 are OFF (b) switching Q4 OFF at a time t 2 to commence said first half-cycle free-wheeling interval; (c) maintaining SR2 in said high impedance state for at least a portion of said first half-cycle freewheeling interval; (d) switching Q3 ON at a time t 3 when the voltage across C3 reaches a desired level; (e) switching Q1 OFF at a time t 4 ; (f) switching Q2 ON at a time t 5 when the voltage across C2 reaches a desired level to commence said second half-cycle on-time; (g) switching Q3 OFF at a time t 6 to commence said second half-cycle free-wheeling interval; (h) maintaining SR1 in said high impedance state for at least a portion of said second half-cycle free-wheeling interval; (i) switching Q4 ON at a time t 7 when the voltage across C4 reaches a desired level; (j) switching Q2 OFF at a time t 8 ; and (k) switching Q1 ON at a time t 9 when the voltage across C1 reaches a desired level to recommence said first half-cycle on-time and to commence a next cycle of converter operation.