Read/write preamplifier with head isolation

Claim 2

A read/write preamplifier configured for interconnection with a magnetic head through head contacts, the preamplifier comprising: a write control switching circuit electrically connected between first and second supply terminals and connected to the head contacts for controlling a first current capable of flowing through the magnetic head in response to a write input signal, the switching circuit including at least one transistor; a first transistor coupled between the first supply terminal and the at least one transistor of the write control switching circuit for controlling a second current capable of flowing to the write control switching circuit so as to cause the switching circuit to be driven to either a selected state or an unselected state with the second current and the first current having substantially different magnitudes; and a bias circuit coupled between the first and second supply terminals and to the first transistor, the bias circuit including a mode-controlled current sink responsive to a mode control signal and causing the first transistor to conduct current and drive ht switching circuit to the selected state when the mode-controlled current sink is active, and causing the first transistor to prohibit current flow and drive the switching circuit to the unselected state when the current sink is inactive.

Claim 3

A read/write preamplifier of claim 1 wherein the first transistor is a PNP-type transistor having an emitter terminal, a collector terminal and a base terminal and wherein the first supply terminal is electrically coupled to the emitter terminal of the first transistor.

Claim 4

A read/write preamplifier of claim 2 wherein the bias circuit is electrically coupled to the base and emitter terminals of the first transistor and in series with the first supply terminal and the mode-controlled current sink.

Claim 5

A read/write preamplifier of claim 3 wherein the bias circuit includes a resistor coupled between the emitter and base terminals of the first transistor.

Claim 6

A read/write preamplifier of claim 3 wherein the bias circuit includes a second PNP-type transistor electrically coupled to the emitter and base terminals of the first transistor to form a current mirror wherein the second current flowing through the first transistor is related to a mirror current flowing through the second PNP-type transistor.

Claim 7

A read/write preamplifier of claim 1 wherein the write control switching circuit further includes an H-switch comprising: upper write switching transistors, each transistor having first and second terminals connected in series with the first supply terminal and the head contacts and having a control terminal electrically connected to receive current from the first transistor with the first transistor being a PNP-type transistor; lower write switching transistors, each transistor having first and second terminals connected in series with the head contacts and the second supply terminal and having a control terminal; and write data control circuitry electrically connected to the control terminals of the upper and lower write switching transistors for operating the upper and lower write switching transistors to control the direction at which the first current flows through the magnetic head.

Claim 8

The read/write preamplifier of claim 6 wherein the first supply terminal operates as a voltage source for the control terminals of the upper write switching transistors.

Claim 9

The read/write preamplifier of claim 6 wherein the second supply terminal operates as a current sink for the second terminals of the lower write switching transistors.

Claim 10

The read/write preamplifier of claim 6 and further comprising: a read amplifier; a read current sink; and a read differential transistor pair, each transistor int he pair having first and second terminals connected in series between the read amplifier and the read current sink and having a control terminal connected to the head contacts.

Claim 11

The read/write preamplifier of claim 9 wherein the second terminals of the upper write switching transistors, int he unselected state, have a high impedance connections with the head contacts and with the control terminals of the read differential transistor pair.

Claim 12

The read/write preamplifier of claim 6 and further comprising voltage biasing circuitry electrically connected between the control terminals of the upper write switching transistors and the first transistor.

Claim 13

The read/write preamplifier of claim 11 wherein the voltage biasing circuitry includes at least one resistor connected between the first transistor and the control terminals of the upper write switching transistors.

Claim 14

The read/write preamplifier of claim 11 wherein the voltage biasing circuitry includes an NPN-type transistor having a control terminal electrically coupled to the collector terminal of the first transistor and an emitter terminal electrically coupled to the control terminals of the upper write switching transistors in such a manner as to create an emitter-follower connection between the NPN-type transistor and the control terminals of the upper write switching transistors.

Claim 15

A read/write preamplifier configured for interconnection with a magnetic head through head contacts, the preamplifier comprising: upper write switching transistors, each transistor having a first terminal, a second terminal, and a control terminal, wherein the first and second terminals are connected in series with a first supply terminal and the head contacts; lower write switching transistors, each transistor having a first terminal, a second terminal, and a control terminal, wherein the first and second terminals are connected in series with the head contacts and second supply terminal; a first PNP-type transistor including a base terminal, a collector terminal and an emitter terminal, wherein the emitter terminal is electrically connected to the first supply terminal and the collector terminal is electrically connected to the upper write switching transistors such that the collector terminal controls current flow into the control terminals of the upper write switching transistors so as to cause the upper write switching transistors to be driven to either a selected state or an unselected state; a bias circuit coupled between the first and second supply terminals and to the emitter and base terminals of the first PNP-type transistor, the bias circuit including a mode-controlled current sink responsive to a mode control signal and causing the first PNP-type transistor to conduct current and drive the upper write switching transistors to the selected state when the mode-controlled current sink is active, and causing the first PNP-type transistor to prohibit current flow and drive the upper write switching transistors to the unselected state when the mode-controlled current sink is inactive; and write data control circuitry electrically connected to the control terminals of the upper and lower write switching transistors to control current flow through the magnetic head in response to a write input signal.

Claim 16

A read/write preamplifier configured for interconnection with a magnetic head through head contacts, the preamplifier comprising: upper write switching transistors, each transistor having a first terminal, a second terminal, and a control terminal, wherein the first and second terminals are connected in series with a first supply terminal and the head contacts; lower write switching transistors, each transistor having a first terminal, a second terminal, and a control terminal, wherein the first and second terminals are connected in series with the head contacts and second supply terminal; a first PNP-type transistor including a base terminal, a collector terminal and an emitter terminal, wherein the emitter terminal is electrically connected to the first supply terminal and the collector terminal is electrically connected to the upper write switching transistors such that the collector terminal controls current flow into the control terminals of the upper write switching transistors so as to cause the upper write switching transistors to be driven to either a selected state or an unselected state; a bias circuit coupled between the first and second supply terminals and to the emitter and base terminals of the first PNP-type transistor, the bias circuit including a mode-controlled current sink responsive to a mode control signal and causing the first PNP-type transistor to conduct current and drive the upper write switching transistors to the selected state when the mode-controlled current sink is active, and causing the first PNP-type transistor to prohibit current flow and drive the upper write switching transistors to the unselected state when the mode-controlled current sink is inactive; and write data control circuitry electrically connected to the control terminals of the upper and lower write switching transistors to control current flow through the magnetic head in response to a write input signal.

Claim 17

The read/write preamplifier of claim 14 wherein the bias circuit includes a resistor coupled between the emitter and base terminals of the first PNP-type transistor and in series with the first supply terminal and the mode-controlled current sink.

Claim 18

The read/write preamplifier of claim 14 wherein the bias circuit includes a second PNP-type transistor electrically coupled to the emitter and base terminals of the first PNP-type transistor in such a manner as to form a current mirror wherein current flowing through the first PNP-type transistor is related to a current flowing through the second PNP-type transistor.

Claim 19

The read/write preamplifier of claim 14 wherein the first supply terminal operates as a voltage source for the control terminals of the upper write switching transistors.

Claim 20

The read/write preamplifier of claim 14 wherein the second supply terminal operates as a current sink for the second terminals of the lower write switching transistors.

Claim 21

The read/write preamplifier of claim 14 and further comprising: a read amplifier; a read current sink; and a read differential transistor pair, each transistor in the pair having first and second terminals connected in series between the read amplifier and the read current sink and having a control terminal connected to the head contacts.

Claim 22

The read/write preamplifier of claim 19 wherein the second terminals of the upper write switching transistors, in the unselected state, have a high impedance connections with the head contacts and with the control terminals of the read differential transistor pair.

Claim 23

The read/write preamplifier of claim 14 wherein the control terminals of the upper write switching transistors are electrically connected to the receive current from the first PNP-type transistor through voltage biasing circuitry.

Claim 24

The read/write preamplifier of claim 21 wherein the voltage biasing circuitry includes at least one resistor connected between the collector terminal of the first PNP-type transistor and the control terminals of the upper write switching transistors.

Claim 25

The read/write preamplifier of claim 21 wherein the voltage biasing circuitry includes an NPN-type transistor having a control terminal electrically coupled to the collector terminal of the first PNP-type transistor, and an emitter terminal electrically coupled to the control terminals of the upper write switching transistors in such a manner as to create an emitter-follower connection between the NPN-type transistor and the control terminals of the upper write switching transistors.

Claim 26

An improved read/write preamplifier of the type having a read differential transistor pair and an H-switch write control circuit with upper write switching transistors, lower write switching transistors and first and second supply terminals, the read differential transistor pair and the upper and lower write switching transistors electrically connected to a read/write magnetic head, the improvement comprising; a first PNP-type transistor having a collector terminal, an emitter terminal and a base terminal, the collector terminal electrically coupled to the upper write switching transistors for controlling base current into each of the upper write switching transistors so as to cause the upper write switching transistors to be driven to either a selected state or an unselected state, the emitter terminal electrically coupled to the first supply terminal; and a bias circuit coupled between the first and second supply terminals and to the emitter and base terminals of the first PNP-type transistor and including a mode controlled current sink responsive to a mode control signal, the bias circuit causing the first PNP-type transistor to conduct current and drive the upper write switching transistors to the selected state when the mode-controlled current sink is active, and causing the first PNP-type transistor to prohibit current flow and drive the upper write switching transistors to the unselected state when the mode-controlled current sink is inactive.

Claim 27

An improved read/write preamplifier of the type having a read differential transistor pair and an H-switch write control circuit with upper write switching transistors, lower write switching transistors and first and second supply terminals, the read differential transistor pair and the upper and lower write switching transistors electrically connected to a read/write magnetic head, the improvement comprising; a first PNP-type transistor having a collector terminal, an emitter terminal and a base terminal, the collector terminal electrically coupled to the upper write switching transistors for controlling base current into each of the upper write switching transistors so as to cause the upper write switching transistors to be driven to either a selected state or an unselected state, the emitter terminal electrically coupled to the first supply terminal; and a bias circuit coupled between the first and second supply terminals and to the emitter and base terminals of the first PNP-type transistor and including a mode controlled current sink responsive to a mode control signal, the bias circuit causing the first PNP-type transistor to conduct current and drive the upper write switching transistors to the selected state when the mode-controlled current sink is active, and causing the first PNP-type transistor to prohibit current flow and drive the upper write switching transistors to the unselected state when the mode-controlled current sink is inactive.

Claim 28

The read/write preamplifier of claim 24 wherein the bias circuit includes a resistor coupled between the emitter and base terminals of the first PNP-type transistor and in series with the first supply terminal and the mode-controlled current sink.

Claim 29

The read/write preamplifier of claim 24 wherein the bias circuit includes a second PNP-type transistor electrically coupled to the emitter and base terminals of the first PNP-type transistor in such a manner as to form a current mirror wherein current flowing through the first PNP-type transistor is related to the current flowing through the second PNP-type transistor.

Claim 30

The read/write preamplifier of claim 24 wherein the upper write switching transistors, in the unselected state, have a high impedance connections with the head contacts and with the read differential transistor pair.

Claim 31

The read/write preamplifier of claim 24 wherein the upper write switching transistors include control terminals that are electrically connected to receive current from the collector terminal of the first PNP-type transistor through voltage biasing circuitry.

Claim 32

The read/write preamplifier of claim 28 wherein the voltage biasing circuitry includes at least one resistor.

Claim 33

The read/write preamplifier of claim 28 wherein the voltage biasing circuitry includes an NPN-type transistor having a control terminal electrically coupled to the collector terminal of the first PNP-type transistor and an emitter terminal electrically coupled to the control terminals of the upper write switching transistors in such a manner as to create emitter-follower connections between the NPN-type transistor and the control terminals of the upper write switching transistors.